• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.711-714
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• 2000

In this paper, we propose a high-speed multiplier-free realization using ROM’s to store the results of coefficient scalings in Combination With higher signal rate and pipelined operations. We show that hardware multipliers are not needed. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or through-put). An example is given comparing the proposed realization with the distributed arithmetic (DA) realization. Results show that With Proper Choices of the Parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2944-2946
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• 1999

In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

• Journal of IKEEE
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• v.15 no.1
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• pp.10-14
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• 2011

In this paper, we present an efficient hardware architecture of unrolling image mapper of catadioptric omnidirectional imaging systems. The catadioptric omnidirectional imaging systems generate images of 360 degrees of view and need to be transformed into panorama images in rectangular coordinate. In most application, it has to perform the panorama unrolling in real-time and at low-cost, especially for high-resolution images. The proposed hardware architecture adopts a software/hardware cooperative structure and employs several optimization schemes using look-up-table(LUT) of coordinate conversion. To avoid the on-line division operation caused by the coordinate transformation algorithm, the proposed architecture has the LUT which has pre-computed division factors. And then, the amount of memory used by the LUT is reduced to 1/4 by using symmetrical characteristic compared with the conventional architecture. Experimental results show that the proposed hardware architecture achieves an effective real-time performance and lower implementation cost, and it can be applied to other kinds of catadioptric omnidirectional imaging systems.

• Journal of IKEEE
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• v.24 no.2
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• pp.497-501
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• 2020

Dehaze is essential for autonomous driving and intelligent CCTV to operate normally even in foggy weather. The method of airlight estimation is particularly important in dehaze technology. In this paper, we propose a patch-based airlight estimation algorithm and hardware structure that can reduce the amount of unnecessary computation and effectively estimate the airlight in various input images. Proposed algorithm is compared with the popular quad-tree method, and the hardware design is implemented by using XILINX's xc7z045-ffg900 target board as a structure that can satisfy to international standard 4K video in real time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.283-290
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• 2006

The cellular neural networks have the structure that consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template properties. So, it has a very suitable structure for the hardware implementation. But, it is impossible to have a one-to-one mapping between the CNN hardware processors and the pixels of the practical large image. In this paper, a $5{\times}5$ CNN hardware processor with pipeline input and output that can be applied to the time-multiplexing processing scheme, which processes the large image with a small CNN cell block, is designed. the operation of the implemented $5{\times}5$ CNN hardware processor is verified from the edge detection and the shadow detection experimentations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of IKEEE
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• v.26 no.2
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• pp.226-231
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• 2022

The concept of information entropy has been widely applied in various fields. Recently, in the field of image processing, many technologies applying the concept of information entropy have been developed. As the importance and demand of computer vision technologies increase in modern industry, real-time processing must be possible in order for image processing technologies to be efficiently applied to modern industries. Extracting the entropy value of an image is difficult to process in real-time due to the complexity of computation in software, and a hardware structure of an image entropy filter capable of real-time processing has never been proposed. In this paper, we propose for the first time a hardware structure of a histogram-based entropy filter that can be processed in real time using a barrel shifter. The proposed hardware was designed using Verilog HDL, and Xilinx's xczu7ev-2ffvc1156 was set as the target device and FPGA was implemented. As a result of logic synthesis using the Xilinx Vivado program, it has a maximum operating frequency of 750.751 MHz in a 4K UHD high-resolution environment, and it processes more than 30 images per second and satisfies the real-time processing standard.

• Journal of the Korea Society of Computer and Information
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• v.28 no.1
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• pp.71-78
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• 2023

In this paper, we analyze the structure of TV video software, one of the warship combat management system software, and propose a standard architecture that minimizes software modification due to the discontinuation replacement of warship hardware. The class structure was newly designed to minimize the class modified when replacing the warship hardware by separating the variable elements and common elements of TV video software through FORM(Feature-Oriented Reuse Method), the common part that communicates with the warship combat management system and displays the TV screen and the variable part that communicates between the operator and the TV camera. In addition, the Strategy design pattern is applied to efficiently add and modify classes that directly use hardware-dependent APIs when replacing hardware discontinuation, and to make both discontinued and replacements available software. Finally, the reliability testing time and functional testing time of the existing TV video software and the proposed software were measured and compared, and finally, it was confirmed that the hardware discontinuation replacement cost was reduced.

• Journal of Korea Game Society
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• v.14 no.6
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• pp.29-38
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• 2014

In the large scale indoor 3D game scenes, the data amount of potentially visible set (PVS) which pre-computes the information of occlusion culling can be huge. However, the large part of them can be represented as zero. In this paper, the effective hardware structure is designed, which compresses PVS data as the way of zero run length encoding (ZRLE) during building the scene trees of 3D games in mobile environments. The compression ratio of the proposed structure and the rendering speed (frame per second: FPS) according to both PVS culling and frustum culling are analyzed under 3D game simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.119-128
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• 2004

In this paper, a low-power 8-point DCT structure is proposed using add and shift operations. Proposed structure adopts 4 cycles for complete 8-point DCT in order to minimize size of hardware and to enable high-speed processing. In the structure, hardware for the first cycle can be shared in the next 3 cycles since all columns in the DCT coefficient matrix are common except sign. Conventional DCT structures implemented with only add and shift operation use CSD(Canonic Signed Digit) form coefficients to reduce the number of adders. To reduce the number of adders further, we propose a new structure using common sub-expression sharing techniques. With this techniques, the proposed 8-point DCT structure achieves 19.5% adder reduction comparison to the conventional structure using only CSD coefficient form.