• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.746-753
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• 2001

In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.6
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• pp.327-334
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• 1985

A new method on the hardware implementation of multi-channel Finite Impulse Response(FIR) digital filter using vector multiplication structure is proposed. The proposed method can reduce the complexity of hardware structure and improve execution speed. The frequency response of four channel digital filter implemented by the above method is quite agreeable with the frquency response simulated by Remez method.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1334-1337
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• 1997

A spacecraft attitude control ground hardware simulator development is discussed in the paper. The simulator is called KT/KARI HILSSAT(Hardware-In-the Loop Simulator Single Axis Testbed), and the main structure consists of a single axis bearing and a satellite main body model on the bearing. The single axis tabel as ans experimental hardware simulator that evaluates performance and applicability of a satellite before evolving and/or confirming a mew or and old control logic used in the KOREASAT is developed. Attitude control of spaceraft by using reaction wheel is performed.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1577-1580
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• 1987

This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.

• Journal of Information Technology Services
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• v.11 no.4
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• pp.171-180
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• 2012

Since software and hardware integration has became a strategic tool for companies to innovate their products, an information system that can comprehensively manage software and hardware integrated product development is critical for the current product development. This paper proposed a product data model that can support modules of related software and hardware parts in Product Data Management(PDM) integrated with Software Configuration Management(SCM). The model allows engineers to define software and hardware product structure independently, and support the integration module that can summon related software and hardware parts to build a comprehensive module for collaboration. Through the integration module, engineers can identify and examine the effectiveness of their design alternatives to other related parts form different disciplines. The product data model was implemented as a prototype PDM system and tested with an example robotics product.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3247-3261
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• 2000

In recent years, as the complexity of signal processmg systems Increases, the needs for dcslgners to mlx up hardware-part and software-part grow more and more considering both performance and cost There exist many algorilhms In C for vanous Signal processung apphcations. We have to translate the algonlhm C to hardware descnptlon language(HDL), If portion or the algonlhm needs to be unplcmenled in hardwarc pari of the syslcm. For this translation. it's dtfftcult to handle dynamic memory allocalion, function calls, pointer manipoJalion. This research shows a design method for a hardware model about recursive calls which was classified into software part of the system previously [or the translation from C to VHDL. The benefits of havlIlg recursive calls m hardware structure can be quite high since provides flexbility in hardware/software partitioming in codesign sysem.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.106-114
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• 2016

In this paper, we propose an efficient integer inverse transform structure for vp9 decoder. The proposed structure is a hardware structure which is easy to control and requires less hardware resources, and shares algorithms for realizing entire DCT(Discrete Cosine Transform), ADST(Asymmetric Discrete Sine Transform) and WHT(Walsh-Hadamard Transform) in vp9. The integer inverse transform for vp9 google model has a fast structure, named butterfly structure. The integer inverse transform for google C model, unlike universal fast structure, takes a constant rounding shift operator on each stage and includes an asymmetrical sine transform structure. Thus, the proposed structure approximates matrix coefficient values for all transform mode and is used to matrix operation method. With the proposed structure, shared operations for all inverse transform algorithm modes can be possible with reduced number of multipliers compared to the butterfly structure, which in turn manages the hardware resources more efficiently.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.615-618
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• 2000

A number of studies have recently been made on hardware for a biological neuron f3r application with information processing functions of neural networks. We have been trying to produce hardware from the viewpoint that development of a new hardware neuron model is one of the important problems in the study of neural networks. In this paper, we first discuss the circuit structure of a pulse-type hardware neuron model with the enhancement-mode MOSFETs (E-MOSFETs). And we construct a pulse-type hardware neuron model using I-MOSFETs. As a result, it is shown that our proposed new model can exhibit firing phenomena even if the power supply voltage becomes less than 1.5[V]. So it is verified that our model is profitable for IC.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.449-450
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• 2007

Evolvable hardware(EHW) is a dynamic field that brings together reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. This paper gives an introduction to the field. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.183-183
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• 2010

3D Display type have software and hardware architecture in generally got low transmittance characteristics and high price product equipment. In this article, specified polarizer adopted MLA type structure have 3D display with hardware configuration and high transmission wide view angle. Method of screen printing type is adopted B/L system with simple structure.