• Journal of Power Electronics
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• 제1권1호
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• pp.48-55
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• 2001

This paper describes a switching-level simulation model and scaled hardware model for SSSC, which is useful for analyzing the dynamic interaction between the SSC and the power transmission system. A detailed simulation model with EMTP was developed to verity the SSSC operation with control system, and its increasing capability of power transmission through the line for a typical one-machine infinite-bus system. The simulation results of the developed model are compared with the experimental results froma scaled model fo 2KVA rating for evaluation the whole system operation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2475-2477
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• 1999

This paper describes a simulation model and scaled hardware model to analyze the dynamic performance of Unified Power Flow Controller, which adjust flexibly the active and reactive power flow through the ac transmission line. The design of control system was developed using vector control method. The results of simulation and scaled hardware test show that the developed control system works accurately. And both models are very effective to analyze the dynamic performance of the Unified Power Flow Controller.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권10호
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• pp.579-586
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• 1999

This paper describes a simulation model and a scaled hardware model to analyze the dynamic performance of Unified Power Flow Controller, which can flexibly adjust the active power flow through the ac transmission line. The design of control system for UPFC was developed using vector control method. The results of simulation and scaled hardware test show that the developed control system works accurately. Both models would be very effective for analyzing the dynamic performance of the Unified Power Flow Controller.

• 대한전기학회논문지:전력기술부문A
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• 제48권5호
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• pp.524-530
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• 1999

This paper describes performance analysis techniques for SSSC using computer simulations with EMPT and experiments with a hardware scaled-model. A switching-level simulation model with EMTP was developed for the SSSC connected in series with the transmission line. The increase of transmission capability and dynamic performance was analyzed with the simulation model. The simulation results were reverified by experimental works with a hardware scaled-model. The developed analysis techniques can be used for designing and evaluating actual system of SSSC.

• 전기학회논문지
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• 제63권12호
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• pp.1640-1648
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• 2014

This paper proposes a switching frequency reduction method for MMC (Modular Multilevel Converter) utilizing redundancy operation of sub-module, which can offer reduction of voltage harmonics and switching loss. The feasibility of proposed method was verified through computer simulations with PSCAD/EMTDC software. Based on simulation analysis, a hardware scaled-model of 10kVA, DC-1000V MMC was designed and manufactured in the lab. Various experiments were conducted to verify the feasibility of proposed method in the actual hardware system. The hardware scaled-model can be effectively utilized for analyzing the performance of MMC according to the modulation scheme and redundancy operation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 A
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• pp.425-433
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• 1999

This paper describes a simulation model and a scaled hardware model to analyze the dynamic performance of Unified Power Flow Controller, which can flexibly adjust the active and reactive power flow through the ac transmission line. The design of control system was developed using vector control method. The results of simulation and scaled hardware test show that the developed control system works accurately. And both models are very effective to analyze the dynamic performance of the Unified Power Flow Controller.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.2079-2081
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• 1998

This paper describes an experimental results to analyze the dynamic characteristics of STATCOM, which is connected to the ac system for improving the voltage stability. The experimental results confirms that the scaled model for STATCOM operates correctly by the conceived control algorithm and properly compensates and regulates the bus voltage at the common connection point.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 추계학술대회 논문집
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• pp.11-12
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• 2014

This paper introduces a scaled hardware model for the 10kVA, 1kV, 11-level MMC (Modular Multilevel Converter), which was manufactured in the lab based on computer simulations with PSCAD/EMTDC. Various experiments were conducted to verify the major operation algorithms of MMC. The hardware scaled-model developed in the lab can be utilized for analyzing the operation analysis and performance evaluation of MMC according to the modulation pattern and redundancy operation scheme.

• 전기학회논문지
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• 제57권6호
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• pp.985-993
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• 2008

This paper proposes a new DFIG(Doubly-Fed Induction Generator) system using matrix converter, which is very effectively used for interconnecting the wind power system to the power grid. The operation of proposed system was verified by computer simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was conformed by experimental works with a laboratory scaled-model of wind power system. The laboratory scaled-model was built using a motor-generator set with vector drive system, and a matrix converter with DSP(Digital Signal Processor). The operation of scaled-model was tested by modeling the specific variable-speed wind turbine using the real wind data in order to make the scaled-model simulate the real wind power system as close as possible. The simulation and experimental results confirm that matrix converter can be applied for the DFIG system.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권3호
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• pp.133-144
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• 2000

Genetic Algorithm(GA) has been known as a method of solving large-scaled optimization problems with complex constraints in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementations of Genetic Algorithm Processors(GAP) are focused on in recent studies. In this paper, a hardware-oriented GA was proposed in order to save the hardware resources and to reduce the execution time of GAP. Based on steady-state model among continuos generation model, the proposed GA used modified tournament selection, as well as special survival condition, with replaced whenever the offspring's fitness is better than worse-fit parent's. The proposed algorithm shows more than 30% in convergence speed over the conventional algorithm in simulation. Finally, by employing the efficient pipeline parallelization and handshaking protocol in proposed GAP, above 30% of the computation speed-up can be achieved over survival-based GA which runs one million crossovers per second (1㎒), when device speed and size of application are taken into account on prototype. It would be used for high speed processing such of central processor of evolvable hardware, robot control and many optimization problems.