• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1003-1006
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• 2005

Vertex shader of GPU in personal computer is advanced in functions as to be half of traditional fixed T&L functions. And, capacity of memory for saving resources to process instructions is unlimited. GPU that can be programmed by programmer is needed for mobile system as well as personal computer. In this paper, we implement software virtual machine for vertex shader using C++ Language. Our goal is designing hardware GPU that can apply to mobile system. The virtual machine consists of nVidia GPU instructions. Input Data to virtual machine is generated by Microsoft fxc compiler. That is to say, Input Data is compiled shader program written in HLSL, Cg, or ASM. The virtual machine will be a reference model for designing hardware GPU and can be used for Testbed to test added or modified instruction.

• 한국디지털정책학회:학술대회논문집
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• 2004.05a
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• pp.355-367
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• 2004

Interest about information infrastructure construction is decayed socially according to arrival of information age, and various information systems is constructed for efficient business processing, customer service improvement in public sector. According to subjective method of performance improvement for information system of public sector and engine that propel information system construction bemuse it is no definite hardware sizing guidelines for introduction or system caterer, is calculating resources scale of information system. Is situation that problem of excess of scale or reduction sizing is happening, and is causing various kinds problem that is waste of information budget and service decline thereby. So, We proposed hardware sizing framework for information system that is applied to information programs.

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.459-464
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• 2009

This paper presents a production information monitoring system as an infrastructure of CIM system in footwear industry. The system is composed of hardware devices of terminal, communication converter, line controller and software for manufacturing processes. A terminal like a scanner is used for shop floor data input and a line controller is used to link between terminal and server. LAN and RS485 are used for connecting hardware components and deliver their information mutually. In the system, real time production information is acquired from information resources such as group of uppers and soles. The collected production information is delivered to a line controller and analyzed. Server receives information from line controller and machines for production management. Production planning information that is machined in the server is delivered to the shop floor and used for the production management of work in process, and used for improvement of productivity in a footwear production company. The implementation of the developed system shows the effectiveness of the system.

• International journal of advanced smart convergence
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• v.1 no.2
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• pp.12-15
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• 2012

Energy costs for operating and cooling computing resources in Cloud infrastructure have increased significantly up to the point where they would surpass the hardware purchasing costs. Thus, reducing the energy consumption can save a significant amount of management cost. One of major approach is removing hardware over-provisioning. In this paper, we propose a technique that facilitates power saving through reducing resource over provisioning based on virtualization technology. To this end, we use dynamic workload shaping to reschedule and redistribute job requests considering overall power consumption. In this paper, we present our approach to shape workloads dynamically and distribute them on virtual machines and physical machines through virtualization technology. We generated synthetic workload data and evaluated it in simulating and real implementation. Our simulated results demonstrate our approach outperforms to when not using no workload shaping methodology.

• ETRI Journal
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• v.34 no.2
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• pp.256-259
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• 2012

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1551-1554
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• 2002

In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for smart card. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a 10240it RSA cryptographic processor based on proposed scheme in IESA system developed for smart card emulating system. As a result, it is shown that proposed architecture contributes to small area and reasonable speed for smart cards.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.34-42
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• 2013

Human faces have been broadly studied in digital image and video processing fields. An appearance-based method, the adaptive boosting learning algorithm using integral image representations has been successfully employed for face detection, taking advantage of the feature extraction's low computational complexity. In this paper, we propose a face-detection postprocessing method that equalizes instantaneous facial regions in an efficient hardware architecture for use in real-time multimedia applications. The proposed system requires low hardware resources and exhibits robust performance in terms of the movements, zooming, and classification of faces. A series of experimental results obtained using video sequences collected under dynamic conditions are discussed.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.123-131
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• 2002

ASC(Avionics System Computer) was developed to control weapon delivery and navigation sensors, and to perform man-machine interface with pilots for XKO-1 aircraft. The data communications between ASC and UFC(Up Front Controller), DC(Data Concentrator) were implemented by RS422 serial data bus. Also, SCIL(Standard Computer Interface Library) was designed to facilitate control and management of the computer hardware resources and is embedded in the ASC. These structures have a merit of noise immunity and a reduction of wire harness for signal lines, and enable OFP(Operational Flight Program) programmers to use the SCIL easily without knowing hardware details. Manufactured system was on installed on XKO-1, and peformed for BIT(Built In Test) and interface test with UFC and DC. The test results show that it meets the system requirements.