• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.25-35
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• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.73-82
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• 2008

There are several approaches for reducing the ROB(Reorder Buffer) complexity in processors. The one technique that makes the simplest ROB ports relies on a distributed implementation that spreads the centralized ROB structure across the functional units(FUs). Each distributed buffers are decided on the size of them by workload of the functional units. The performance of the processor depends on the size of distributed ROB. However, most of previous works have depended on the simulation results to decide the optimsize of distributed ROB. In this Paper, we use an analytical model based on the M/M/1 Queuing theory to determine the optimum size of each distributed ROB. Our schemes are evaluated by using the simulation performed by the CPU2000 benchmarks. We are able to choose the optimum size of distributed ROB showing the 99.2% performance compared with existing superscalar processors. We can save 82% hardware resources in ports and reduce more than 30% of delay when ROB and distributed ROB proposed in this paper are designed by HDL.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.335-344
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• 2009

Embedded systems and web browsers have started to provide two-dimensional vector graphics features, to finally support scalability of graphics outputs, while traditional graphics systems have focused on the raster and bitmap operations. Nowadays, SVG and Flash are actively used while OpenVG from Khronos group plays the role of a de facto low-level API standard to support them. In this paper, we represent the design and implementation process and the final results of an OpenVG implementation, AlexVG. From its design stage, our implementation aims at the cooperation with SVG-Tiny, another de facto standard for embedded systems. Currently, our overall system provides not only the OpenVG core features but also variety of OpenVG application programs and SVG-Tiny media file playing capabilities. For the conformance with the standard specifications, our system completely passed the whole OpenVG conformance test suites and the graphics output portions of the SVG-Tiny conformance test suites. From the performance point of view, we focused on the efficiency and effectiveness especially on the mobile phones and embedded devices with limited resources. As the result, it showed impressive benchmarks on the small-scale CPU's such as ARM's, even without neither any other libraries nor acceleration hardware.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.269-277
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• 2007

Wireless sensor network system is expected to get high attention in research for now and future owing to the advanced hardware development technology and its various applicabilities. Among variety of sensor network systems, the seashore and marine sensor network, which are extended to get sampling of marine resources, environmental monitoring to prevent disaster and to be applied to the area of sea route guidance. For these marine applications to be available, however, the provision of precise location information of every sensor nodes is essential. In this paper, the sequential localization algorithm for obtaining the location information of marine sensor nodes. The sequential localization is done with the utilization of a small number of beacon nodes along the seashore and gets the location of nodes by controling the sequences of localization and also minimizes the error accumulation. The key idea of this algorithm for localization is that the localization priority of each sensor nodes is determined by the number of reference nodes' information. This sequential algorithm shows the improved error performance and also provide the increased coverage of marine sensor network by enabling the maximum localization of sensor nodes as possible.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.278-281
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• 2018

The early Web technology was to show text information through a browser. However, as web technology advances, it is possible to show large amounts of multimedia data through browsers. Web technologies are being applied in a variety of fields such as sensor network, hardware control, and data collection and analysis for big data and AI services. As a result, the standard has been prepared for the Internet of Things, which typically controls a sensor via HTTP communication and provides information to users, by installing a web browser on the interface of the Internet of Things. In addition, the recent development of web-assembly enabled 3D objects, virtual/enhancing real-world content that could not be run in web browsers through a native language of C-class. Factors that evaluate the performance of existing Web applications include performance, network resources, and security. However, since there are many areas in which web applications are applied, it is time to revisit and review these factors. In this thesis, we will conduct an analysis of the factors that assess the performance of a web application. We intend to establish an indicator of the development of web-based applications by reviewing the analysis of each element, its main points, and its needs to be supplemented.

• Journal of the Korea Society of Computer and Information
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• v.12 no.5
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• pp.103-112
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• 2007

In this paper, we implement a hypervisor that runs multiple uC/OS-II real-time kernels on one microprocessor. The hypervisor virtualizes microprocessor and memory that are main resources managed by uC/OS-II kernel. Microprocessor is virtualized by controlling interrupts that uC/OS-II real-time kernel handles and memory is virtualized by partitioning physical memory. The hypervisor consists of three components: interrupt control routines that virtualize timer interrupt and software interrupt, a startup code that initializes the hypervisor and uC/OS-II kernels, and an API that provides communication between two kernels. The original uC/OS-II kernel needs to be modified slightly in source-code level to run on the hypervisor. We performed a real-time test and an independent computation test on Jupiter 32-bit EISC microprocessor and showed that the virtualized kernels run without problem. The result of our research can reduce the hardware cost, the system space and weight, and system power consumption when the hypervisor is applied in embedded applications that require many embedded microprocessors.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Korean Journal of Construction Engineering and Management
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• v.10 no.6
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• pp.3-12
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• 2009

In order to effectively distribute the resources, it is very critical to understand the status or progress of construction site quickly and accurately. Augmented Reality (AR) can provide this situation with information which is convenient and intuitive. Conventional implementation of AR in outdoor or construction site condition requires additional sensors or markers to track the position and direction of camera. This research is aimed to develop the technologies which can be utilized in gathering the information of constructing or constructed buildings and structures. The AR technique that does not require additional devices except for the camera was implemented to simplify the system and improve utility in inaccessible area. In order to do so, the position of camera's perspective center and direction of camera was estimated using exterior orientation techniques. And 3D drawing model of building was projected and overlapped using this information. The result shows that by using this technique, the virtual drawing image was registered on real image with few pixels of error. The technique and procedure introduced in this paper simplifies the hardware organization of AR system that makes it easier for the AR technology to be utilized with ease in construction site. Moreover, this technique will help the AR to be utilized even in inaccessible areas. In addition to this, it is expected that combining this technique and 4D CAD technology can provide the project manager with more intuitive and comprehensive information that simplifies the monitoring work of construction progress and planning.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.623-628
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• 2009

The emergence of compact and low-power wireless communication sensors and actuators in the technology supporting the ongoing miniaturization of processing and storage allows for entirely the new kinds of embedded systems. These systems are distributed and deployed in environments where they may have been designed into a particular control method, and are often very dynamic. Collection of devices can communicate to achieve a higher level of coordinated behavior. Wireless sensor nodes deposited in various places provide light, temperature, and activity measurements. Wireless sensor nodes attached to circuits or appliances sense the current or control the usage. Together they form a dynamic and multi-hop routing network connecting each node to more powerful networks and processing resources. Wireless sensor networks are a specific-application and therefore they have to involve both software and hardware. They also use protocols that relate to both applications and the wireless network. Wireless sensor networks are consumer devices supporting multimedia applications such as personal digital assistants, network computers, and mobile communication devices. Wireless sensor networks are becoming an important part of industrial and military applications. The characteristics of modem embedded systems are the capable of communicating adapting the different operating environments. In this paper, We designed and implemented sensor network system which shows through host PC sensing temperature and humidity data transmitted for wireless sensor nodes composed wireless temperature and humidity sensor and designs sensor nodes using embedded system with the intention of studying USN.