• The Korean Journal of Community Living Science
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• v.16 no.1
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• pp.37-47
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• 2005

Education has been emphasized as one of tools of realizing social equality, which has its base on the ideology of equal education opportunity. The Opportunity level of adult education is important in the meaning of social equality. but these days It is being inequality. so The objectives of this study were 1) measuring the opportunity level of adult education in Korea, 2) analysing the difference adult education level by gender, regions, 3) making out the gap of the its level by social educational agencies, 4) to suggest the way to improve the opportunity level of adults educations between adults by gender, regions. The followings are the results from the study: Adult education participation level were lower. Adult education participation level per adult education type showed higher participation at private institutes, lower at cultural center of community and school's human and material resources are not properly utilized in adult educational activities. By adult education participation level per gender and location, women have a higher participation level then men, and urban areas have a higher participation level then rural areas. In case of location, environment variables is most explanatory in adult education participation level. To strive for methods to activate school-oriented adult education activities and to develop political solution to ease the resources gaps for adult education investment among regions in order not to deepen environment gaps of adult education between urban and rural areas. For adult education activation, institution and bodies in charge of adult education should expand and discover hardware and develop and distribute software. Also, adult education specialists who operate and manage these hardware and sofeware efficiently should be recruited.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.233-239
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• 2001

Among the operations in frequency domain for ADSL G.LITE Modem to perform, FFT and FEQ are most computation-intensive part, of which many researches have been focused on the efficient implementation. Previous papers suggested hardwares suitable for ADSL G.DMT system, which is not feasible for simple G.LITE system. The analysis of frequency domain operations and computational efficiency according to the allocation of hardware resources is performed in this paper. The suggested processor has the structure of one real multiplier and two real adders connected in parallel, which can perform the operations efficiently through the pipeline- and/or parallel-type job scheduling. The suggested processor uses less hardware resources than Kiss\`s ALU structure or FFT/IFFT processor suggested by Wang, so the suggested one is more suitable for G.LITE system than previous works.

• KNOM Review
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• v.21 no.2
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• pp.26-34
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• 2018

With the proliferation of cloud computing and services, the internet traffic and the demand for better quality of service are increasing. For this reason, server virtualization and network virtualization technology, which uses the resources of internal servers in the data center more efficiently, is receiving increased attention. However, the existing hardware Test Access Port (TAP) equipment is unfit for deployment in the virtual datapaths configured for server virtualization. Virtual TAP (vTAP), which is a software version of the hardware TAP, overcomes this problem by duplicating packets in a virtual switch. However, implementation of vTAP in a virtual switch has a performance problem because it shares the computing resources of the host machines with virtual switch and other VMs. We propose a vTAP implementation technique based on the extended Berkeley Packet Filter (eBPF), which is a high-speed packet processing technology, and compare its performance with that of the existing vTAP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.12
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• pp.2213-2220
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• 2017

This paper proposes an efficient approach for hardware implementation of moving object detection (MOD) processor using effective Gaussian mixture learning (EGML)-based background subtraction method. Arithmetic units used in background generation were implemented using LUT-based approximation to reduce hardware complexity. Hardware resources used for both background subtraction and Gaussian probability density calculation were shared. The MOD processor was verified by FPGA-in-the-loop simulation using MATLAB/Simulink. The MOD performance was evaluated by using six types of video defined in IEEE CDW-2014 dataset, which resulted the average of recall value of 0.7700, the average of precision value of 0.7170, and the average of F-measure value of 0.7293. The MOD processor was implemented with 882 slices and block RAM of $146{\times}36kbits$ on Virtex5 FPGA, resulting in 60% hardware reduction compared to conventional design based on EGML. It was estimated that the MOD processor could operate with 75 MHz clock, resulting in real-time processing of $800{\times}600$ video with a frame rate of 39 fps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.713-720
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• 2012

Recently, holography has received much attention as the next generation visual technology. Hologram is obtained by the optical capturing, but in recent years it is mainly produced by the method using computer. This method is named by computer generated hologram (CGH). Since CGH requires huge computational amount, if it is implemented by S/W it can't work in real time. Therefore it should use FPGA or GPU for real time operation. If it is implemented in the type of H/W, it can't obtain the same quality as S/W due to the bit limitation of the internal system. In this paper, we analyze the bit width for minimizing the degradation of the hologram and reducing more hardware resources and propose guidelines for H/W implementation of CGH. To do this, we performs fixed-points simulations according to main internal variables and arithmetics, analyze the numerical and visual results, and present the optimal bit width according to application fields.

• Journal of the Korea Furniture Society
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• v.18 no.2
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• pp.91-99
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• 2007

Modernity which is superficial phenomenon set off the mass scale for mass consumption and provide uniformly artificial environment. But natural destruction, environment pollution, resources exhaustion and so on has been caused by this and now ecology is threatened by destruction and damage beyond the limitation and human beings survival is even threatened. Accordingly furniture development for environment preservation considered environment problem is the urgent real situation. Recent paradigm is the concept of Eco-design which is the green design possible to live together in symbiosis, and new types of alternative furniture are needed in Korea as well. 'Furniture for disassembly' is presented as new method for alternative furniture. Furniture for disassembly can be presented by mainly two directions. The first main characteristic is what is assembled by the use of woodworking joints technique as an assembly structure system without any hardware. The second is what is presented as the structure possible to be assembled by simple manual tools with hardware without any glue. The advantages of furniture for disassembly are environment preservation, space application, transportation efficiency and shapeliness. In manufacture method which is different from present furniture, the application of traditional truss technique which uses various types of custom-made and connection technique in case of assemble structure system without hardware is the typical differences. This assembly method expects not only interest induction about assembly and disassembly of diagram per sub materials but also the development of emotion, the improvement of collaboration, space perception ability and shape sense, the improvement of solid body structure insight and so on, when it use in the furniture for children with the application to many kinds of structure with BANGDOOSANJ (Wedged), JUMUGJANGBU (Dovetail) or NABIEUNJANG (Dovetail Keys) and so on.

• Spatial Information Research
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• v.23 no.4
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• pp.1-11
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• 2015

Since the Spatial Information Open Platform service started in January 2012, the number of service users and the size of the system has increased significantly. However, we could not know the analysis result about how much the hardware resources of the Open Platform system can handle user services. Thereafter, whenever the number of service users are rapidly increased, we simply have solved the service delays using the hardware extension. So, this study presents the obvious solution to avoid the same problem in the future, by pinpointing the system performance of the Open Platform. In this study, through the performance analysis of hardware using NMON and the load test of web service using nGrinder, we intend to get an accurate performance of the Open Platform system. Then we intend to present the resource reallocation method in order to provide better performance of the system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.59-68
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• 2002

In this paper, we design the two-dimensional Discrete Wavelet Transform (2D DWT) filter that is widely used in various applications such as image compression because it has no blocking effects and relatively high compression rate. The filter that we used here is two-channel four-taps QMF(Quadrature Mirror Filter) Lattice filter with PR (Perfect Reconstruction) property. The proposed DWT architecture, with two consecutive inputs shows an efficient performance with a minimum of such hardware resources as multipliers, adders, and registers due to a simple scheduling. The proposed architecture was verified by the RTL simulation, and utilizes the hardware 100%. Our architecture shows a relatively high performance with a minimum hardware when compared with other approaches. An efficient memory mapping and address generation techniques are introduced and the fixed-point arithmetic analysis for minimizing the PSNR degradation due to quantization is discussed.

• Journal of IKEEE
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• v.19 no.1
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• pp.45-51
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• 2015

Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.

• Smart Media Journal
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• v.3 no.4
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• pp.16-21
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• 2014

HEVC is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264 high profile. Intra prediction has 35 directional modes including dc and planer. However an accurate mode decision on lots of modes with SSE is too costly to implement it with hardware. The key idea of this paper is a DCT shared architecture to reduce the complexity of HEVC intra encoder. It is to use same DCT block to quantize as well as to calculate SSE in RDO. The proposed intra encoder uses two step mode decision to lighten complexity with simplified RDO blocks and shares the transform resources. Its BD-rate increase is negligible at 20% on hardware aspect and the operating clock frequency is 300MHz@60fps on FHD ($1920{\times}1080$) image.