• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.129-140
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• 1994

In this paper we investigate the hardware implementation of block matching algorithms (BMAs) for moving sequences. Using systolic arrays we propose a hardware architecture of a two-stage BMA using integral projections which reduces greatly computational complexity with its performance comparable to that of the full search (FS). Proposed hardware architecture is faster than hardware architecture of the FS by 2~15 times. For realization of the FS and two stage BMA modeling and simulation results using SPW and VHDL are also shown.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.317-320
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• 2002

In this paper, we will present the design and implementation of the KASUMI crypto algorithm and confidentiality algorithm (f8) to an hardware chip for 3GPP system. The f8 algorithm is based on the KASUMI which is a block cipher that produces a 64-bit output from a 64-bit input under the control of a 128-bit key. Various architectures (low hardware complexity version and high performance version) of the KASUMI are made with a Xilinx FPGA and the characteristics such as hardware complexity and thor performance are analyzed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.162-167
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• 1994

The binary image normalization method in image processing can be used in several fields, Especially, its high speed processing method and its hardware implmentation is more useful, A normalization process of each character in character recognition requires a lot of processing time. Therefore, the research was done as a part of high speed process of OCR (optical character reader) implementation as a pipeline structure with host computer in hardware to give temporal parallism. For normalization process, general purpose CPU,MC68000, was used to implement it. As a result of experiment, the normalization speed of the hardware is sufficient to implement high speed OCR which the recognition speed is over 140 characters per second.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.201-202
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• 2006

In this paper, we achieved software and hardware implementation of SHA-1 hash function for sensor network. We implemented the software to be compatible with TinySec. In hardware design, we optimized operation logics for small area of hardware and minimized data transitions of register memory for low power design. Designed the software and hardware is verified on commercial sensor motes and our secure motes respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.12
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• pp.1153-1159
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• 2007

This paper presents the hardware implementation of nonlinear PID controllers for the ROBOKER humanoid robot arms. To design the nonlinear PID controller on an FPGA chip, nonlinear functions as well as the conventional PID control algorithm have to be implemented by the hardware description language. Therefore, nonlinear functions such as trigonometric or exponential functions are designed on an FPGA chip. Simulation studies of the position control of humanoid arms are conducted and results are compared. Superior performances by the nonlinear PID controllers are confirmed when disturbances are present. Experiments of humanoid robot arm control tasks are conducted to confirm the performance of our hardware design and the simulation results.

• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.212-218
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• 2022

The performance of vision-based intelligent systems, such as self-driving cars and unmanned aerial vehicles, is subject to weather conditions, notably the frequently encountered haze or fog. As a result, studies on haze removal have garnered increasing interest from academia and industry. This paper hereby presents a 4K-capable hardware implementation of an efficient haze removal algorithm with the following two improvements. First, the depth-dependent haze distribution is predicted using a linear model of four haze-relevant features, where the model parameters are obtained through maximum likelihood estimates. Second, the approximated quad-decomposition method is adopted to estimate the atmospheric light. Extensive experimental results then follow to verify the efficacy of the proposed algorithm against well-known benchmark methods. For real-time processing, this paper also presents a pipelined architecture comprised of customized macros, such as split multipliers, parallel dividers, and serial dividers. The implementation results demonstrated that the proposed hardware design can handle DCI 4K videos at 30.8 frames per second.

• Journal of IKEEE
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• v.22 no.4
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• pp.901-906
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• 2018

Due to the development of display technologies for images, the resolution and quality of images are increasing day by day. In accordance with the development of the display technology, researches have been actively conducted on technologies for converting and displaying existing images to higher resolution and quality. Since the results of theses studies are included in the image signal processor, hardware implementation is indispensable. In this paper, we propose a real-time HDR(High Dynamic Range) conversion hardware implementation of LDR(Low Dynamic Range) image using luminance distribution. The proposed method extracts the features of the image using the histogram of the luminance distribution, and extends the luminance and color based on the extracted features. In addition, when the proposed method is designed by hardware IP(Intellectual Property) and its performance is verified, 4K DCI(Digital Cinema Image) can be handled at a rate of 30fps at 265.46MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.999-1002
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• 2013

There are numerous image processing systems these are usually depend on high performance processors. However, systems using high performance processors might not be proper to mobile applications or low-power systems. Therefore, more efficient methodology for image processing is required for variable applications. This paper proposed pre-processing method using intra prediction concept in order to reduce processing range in a image picture(frame) and entire processing time. Also, the system configuration based on intra prediction hardware core and implementation result of the hardware core are presented in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• Journal of IKEEE
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• v.23 no.3
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• pp.978-983
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• 2019

Under the influence of Autonomous Driving and AI, it is important to accurately recognize and judge objects through cameras. In particular, since a method of recognizing an object using a camera can obtain a large amount of information visually compared to other methods, many image signal processing methods have been studied to extract an accurate image. In addition, a lot of research is being carried out to implementation about hardware. In this work, we compare the principles and characteristics of the sorting algorithms that are frequently used in image signal processing and summarize the performance evaluation. Based on this, we define an efficient algorithm when implemented in hardware among efficient sorting algorithms.