• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2001.12a
• /
• pp.255-258
• /
• 2001

This paper is implementation of cellular automata neural network system which is a living creatures' brain using evolving hardware concept. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogeny of natural living things. The proposed system developes each cell's state in neural network by CA. And it regards code of CA rule as individual of genetic algorithm, and evolved by genetic algorithm. In this paper we implement this system using evolving hardware concept Evolving hardware is reconfigurable hardware whose configuration is under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system is verified by applying it to time-series prediction.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.1B
• /
• pp.40-52
• /
• 2007

Mobile IP allows mobile end-systems to maintain on-going connections while moving to other links. Based on the Internet Protocol Version 6 (IPv6), mobile IPv6 provides a set of new mobility functions such as route optimization in addition to the functions in mobile IPv4. This paper describes the hardware-based mobile IPv6 implementation which provides all the mobility functionalities in hardware. The hardware-based mobile IPv6 provides faster mobility support than software-based implementation as well as it reduces the number of packet losses which can be caused during the movement. In end-systems equipped with hardware-based mobility support, the CPU can concentrate more on running application programs without wasting its effort for mobility support, and hence it is expected the overall performance improvement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.05a
• /
• pp.466-468
• /
• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• ETRI Journal
• /
• v.33 no.4
• /
• pp.611-620
• /
• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.5
• /
• pp.718-723
• /
• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• ETRI Journal
• /
• v.27 no.5
• /
• pp.557-562
• /
• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.473-476
• /
• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• Proceedings of the KIEE Conference
• /
• 1987.07a
• /
• pp.265-269
• /
• 1987

In an industrial vision system, a coding technique for binary image is essential to extract useful informations. To reduce the processing time, a hardware implementation of the chain coding algorithm is attemped. For that purpose, the chain coding algorithm is modified so that it is more suitable for a hardware implementation. A hardwired chain coder is also developed and tested with developed vision system. The result shows that the processing time is greatly reduced and that the developed vision system is maybe feasible for real-time applications.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.852-855
• /
• 2003

This paper reports the RFC(Recursive Flow Classification) algorithm that is available on multiple fields. It is easy to be implemented by both software and hardware. For high speed classification of packets, the implementation of RFC is essential by hardware. Hence, in this paper, RFC algorithm is simulated by Verilog-HDL, and it verify the efficiency of the algorithm. The result shows that the algorithm can perform a packet classification within several cycles. It is not only much faster than software implementation but also enough to support OC192c.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.509-513
• /
• 2004

An area of research called evolvable hardware (EHW) has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. This paper gives an introduction to the field. It continues by including classifying the EHW and the applications of the area.