• ETRI Journal
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• v.35 no.1
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• pp.18-26
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• 2013

This paper proposes an efficient bandwidth utilization (EBU) algorithm that utilizes the unused bandwidth in dynamic bandwidth allocation (DBA) of a 10-gigabit-capable passive optical network (XGPON). In EBU, an available byte counter of a queue can be negative and the unused remainder of an available byte counter can be utilized by the other queues. In addition, EBU uses a novel polling scheme to collect the requests of queues as soon as possible. We show through analysis and simulations that EBU improves performance compared to that achieved with existing methods. In addition, we describe the hardware implementation of EBU. Finally we show the test results of the hardware implementation of EBU.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.76-84
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• 2020

Neuromorphic hardware refers to brain-inspired computers or components that model an artificial neural network comprising densely connected parallel neurons and synapses. The major element in the widespread deployment of neural networks in embedded devices are efficient architecture for neuromorphic hardware with regard to performance, power consumption, and chip area. Spiking neural networks (SiNNs) are brain-inspired in which the communication among neurons is modeled in the form of spikes. Owing to brainlike operating modes, SNNs can be power efficient. However, issues still exist with research and actual application of SNNs. In this issue, we focus on the technology development cases and market trends of two typical tracks, which are listed above, from the point of view of artificial intelligence neuromorphic circuits and subsequently describe their future development prospects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.185-192
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• 2010

This paper presents a hardware-efficient auto-correlation scheme for the synchronization of MIMO-OFDM based wireless local area network (WLAN) systems, such as IEEE 802.11n. Carrier frequency offset (CFO) estimation for the frequency synchronization requires high complexity auto-correlation operations of many training symbols. In order to reduce the hardware complexity of the MIMO-OFDM synchronization, we propose an efficient correlation scheme based on time-multiplexing technique and the use of reduced samples while preserving the performance. Compared to a conventional architecture, the proposed architecture requires only 27% logic gates and 22% power consumption with acceptable BER performance loss.

• Journal of Korea Multimedia Society
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• v.9 no.12
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• pp.1617-1627
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• 2006

The concept of middleware for digital TV receivers is not new one. Using middleware for digital TV development has a number of advantages. It makes it easier for manufacturers to hide differences in the underlying hardware. It also offers a standard platform for application developers. Digital TV middleware enables set-top boxes(STBs) to run video, audio, and applications. The main concern of digital TV middleware is now to reduce its memory usage because most STBs in the market are small footprint. In this paper, we propose several ideas about how to reduce the required memory size on the runtime area of DTV middleware using a new native process technology. Our proposed system has two components; the Efficient Native Process Module, and Enhanced Native Interface APIs for concurrent native modules. With our approach, the required memory reduced from 50% up to 75% compared with the traditional approach. It can be suitable for low end STBs of very low hardware limitation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3256-3264
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• 1996

This paper presents an efficient VLSI architecture for transposing matris in high speed. In the case of transposing N*N matrix, N$^{2}$ numbers of transposition cells are configured as regular and spuare shaped structure, and pipeline structure for operating each transposition cell in paralle. Transposition cell consists of register and input data selector. The characteristic of this architecture is that the data to be transposed are divided into several bundles of bits, then processed serially. Using the serial transposition of divided input data, hardware complexity of transpositioncell can be reduced, and routing between adjacent transposition cells can be simple. the proposed architecture is designed and implemented with 0.5 .mu.m VLSI library. As a result, it shows stable operation in 200 MHz and less hardware complexity than conventional architectures.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.297-300
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• 2000

This paper proposes a high-speed and area-efficient FFT algorithm and performs a hardware implementation. This algorithm, named by “Radix-4/2”, uses the feature of existing radix-2$^3$algorithm, It reduces the number of non-trivial multipliers in SFG to the ratio of 3 to 2 campared with radix-2 or radix-4 algorithm and radix-4/2 has also twice throughput as radix-2$^3$algorithm's. It is proved that FFT processor using the proposed algorithm and 64-point MDC pipeline architecture has twice throughput as radix-2$^3$algorithm's, and reduces areas by 25 percentages in contrast to radix-4 algorithm's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.1-13
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• 1995

In this paper, a specification for wireless LAN MODEM using direct sequence spread spectrum (DS/SS) technique is presented. Some algorithms and hardware architectures for an efficient implementation of the DS/SS MODEM are suggested. In the method, all baseband signal processing are done digitally for single chip implementation. Schemes of DQPSK baseband modulation/demodulation, despreading with digital matched filter, digital timing recovery, and efficient carrier sensing are among the discussed algorithms. We also performed various kinds of simulations to evaluate the system performance and to extract parameters for hardware implementation. In addition, the pictorial view of ASIC of the SS MODEM is also shown.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.69-72
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• 1999

In this paper, an efficient time domain equalization algorithm for discrete wavelet multitone(DWMT) data transmission is developed. In this algorithm, the time domain equalizer(TEQ) consists of two stages, i.e., the channel impulse response shortening equalizer(TEQ-S) in the first stage and the channel frequency flattening equalizer(TEQ-F) in the second stage. TEQ-S reduces the length of transmission channel impulse response to decrease intersymbol interference(ISI) followed by TEQ-F that enhances the channel frequency response characteristics to the level of an ideal channel, hence diminishes the bit error rate. TEQ-S is implemented using the least-squares(LS) method, while TEQ-F is designed by using the least mean-square(LMS) algorithm. Since DWMT system also requires of the frequency domain equalizer in order to further reduce ICI and ISI the hardware complexity is an another concern. However, by adopting an well designed and trained TEQ, the hardware complexity of the whole DWMT system can be greatly reduced.