• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1182-1191
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Alters FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.663-674
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• 2003

Bump mapping is a technique that represents the detailed parts of the object surface, such as a perturberance of the skin of a peanut, using the geometry mapping without complex modeling. However, the hardware implementation for bump mapping is considerable, because a large amount of per pixel computation, including the normal vector shading, is required. In this paper, we propose a new bump mapping algorithm using the polar coordinate system and its hardware architecture. Compared with other existing architectures, our approach performs bump mapping effectively by using a new vector rotation method for transformation into the reference space and minimizing illumination calculation. Consequently, our proposed architecture reduces a large amount of computation and hardware requirements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.926-932
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• 2007

Various research groups proposed various architecture of hardware VPN for the high performance VPN system. However, the VPN based on hardware researcher are focused only on the encryption acceleration. Soft based VPN is only useful when the network connection is slow. We have to consider the hardware performance (encryption/decryption processing capability, packet processing, architecture method) to implement hardware based VPN. In this paper, we have analysed architecture of hardware, consideration and problems for high-speed VPN system, From the result, we can choose the proper design guideline.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.472-475
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• 2005

This paper present a robot controller developed for shipbuilding yard. Since shipbuilding process handles large work pieces and has dusty and noisy environment, the developed controller has separated architecture into main control part and servo control part. Main control part is located in control room while servo control part is located near robot with work pieces. Commutation between two parts is done through SynqNet and RS485. Air purging system is adapted to servo control part for better reliability. We aimed open architecture in both hardware and software architecture. For open hardware architecture, we employed Compact PCI (cPCI) because it is widely used bus system and very reliable. Since lots of commercial boards are available with cPCI interface, upgrade and reconfiguration is easy. For open software architecture, Windows XP�� Embedded is selected as operating system (OS), because it is very popular OS and most hardware vender supports device driver for the windows XP.

• Journal of the Korea Computer Graphics Society
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• v.23 no.3
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• pp.55-64
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• 2017

In this paper, a novel soft shadow method is suggested to support realistic shadows in mobile ray tracing. In ray tracing, soft shadow is generally generated by sampling a shadow ray. As this sampling method increases the number of rays to be processed, it has undermined the performance. We designed the proposed soft shadow processing method and hardware architecture to overcome this problem through selective shadow generation and triangle address caching for minimizing the performance degradation caused by sampling. The proposed hardware architecture can be integrated into a mobile ray-tracing hardware and was evaluated in terms of its performance on the FPGA. Based on the results, the rendering performance about 4, 8, and 16 samples were improved, respectively, by 40%, 50%, and 56% on average compared to the previous method, and it was found that the real-time soft shadow processing is feasible with the proposed hardware architecture.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.423-428
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• 2007

Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.11
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• pp.1094-1103
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• 2014

In this paper, we survey the works related to the system architecture of avionics and extract characteristics from the related works. On the basis of the investigation, we propose an integrated modular avionics (IMA) architecture that can be used for current avionic upgrades and future avionic developments based on the IMA Core system. To verify the feasibility of the proposed IMA architecture, we have developed the prototype of the IMA Core system that consists of both the common hardware module and the IMA software. It was verified that the developed prototype with the common hardware module contributes to the improvement of maintainability because it can save the time and expenses for the development and can reduce the number of types of hardware modules when compared with Federated architecture. It was also confirmed that the developed prototype can save not only overall system weight, size, and power consumption but also the number of hardware types because the IMA software can support the integrated processing where the single processing hardware module can process multiple software applications.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.14-18
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• 2003

This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50％ up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1553-1557
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• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.