• Journal of Aerospace System Engineering
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• v.8 no.2
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• pp.21-26
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• 2014

The aircraft manufacturers are constantly driving to reduce manufacturing lead times and cost at the same time as the product complexity increases and technology continues to change. Integrated Modular Avionics (IMA) is a solution that allows the aviation industry to manage their avionics complexity. IMA defines an integrated system architecture that preserves the fault containment and 'separation of concerns' properties of the federated architectures. In software side, the air transport industry has developed ARINC 653 specification as a standardized Real Time Operating System (RTOS) interface definition for IMA. It allows hosting multiple applications of different software levels on the same hardware in the context of IMA architecture. This paper describes a study that provided the avionics software design for separation of fault and backup of core function to reduce workload of pilot with cost efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.44-52
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• 2006

Recently developed MPEG-4 Part 2 compression standard provides a novel capability to handle arbitrary video objects. To support this capability, an efficient object segmentation technique is required. This paper proposes a real-time algorithm for foreground object segmentation in video sequences. The proposed algorithm consists of two steps: the first step that segments a video frame into multiple sub-regions using Spatio-Temporal Watershed Transform and the second step in which a foreground object segment is extracted from the sub-regions generated in the first step. For real-time processing, the algorithm is partitioned into hardware and software parts so that computationally expensive parts are off-loaded from a processor and executed by hardware accelerators. Simulation results show that the proposed implementation can handle QCIF-size video at 15 fps and extracts an accurate foreground object.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.177-182
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• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.

• Journal of the Korea Society of Computer and Information
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• v.15 no.9
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• pp.1-8
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• 2010

The key challenge in HW/SW co-design is how to choose the appropriate HW/SW partitioning from the vast array of possible options in the mapping set. In this paper we present a unique and efficient approach for addressing this problem known as Customized Heuristic Algorithm for Reducing Mapping Sets(CHARMS). CHARMS uses sensitivity to individual task computational complexity as well the computed weighted values of system performance influencing metrics to streamline the mapping sets and extract the most optimal cases. Using H.263 encoder, we show that CHARMS sieves out 95.17% of the sub-optimal mapping sets, leaving the designer with 4.83% of the best cases to select from for run-time implementation.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.24-26
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• 2000

본 논문에서는 FDS를 응용한 하드웨어 분할 방법을 강 제약 조건을 만족하면서 FDS를 응용하는 방법보다 낮은 복잡도의 분할 알고리즘을 제안한다. 기존의 FDS 응용 방법은 힘값 계산에서 종속성에 의해 후위 연산이 받는 영향값을 계산하여야 하므로 이로 인한 시간 복잡도가 가중되었다. 본 논문에서는 이러한 복잡도를 저하시키기 위해 노드의 분포 그래프와 구현에 소요되는 비용, 그리고 해당 파티션에서의 실행시간 등에 의해 상대적 긴박도를 정의하여 분할을 수행하지만, 종속성 검사는 종속성 제약조건에 의한 분포그래프의 변화와 스케쥴에 대해서만 고려되며 힘값 계산에는 고려하지 않는다. 또한, 분할 단계에서 스케쥴링을 함께 고려함으로써 합성 이후에 재 스케쥴링의 부하를 경감할 수 있도록 하였다. 제안 알고리즘 결과는 ILP 결과와 비교 분석하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.10b
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• pp.965-968
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• 2000

통합설계에서 제약사항을 만족하는 최적의 시스템을 구현하기 위해 시스템을 기술하는 각 부분을 하드웨어부와 소프트웨어부로 나누어 매핑의 권역을 찾는 분할은 중요한 문제이다. 기존의 분할 알고리즘들[1]은 파티션과 스케줄링을 2단계로 분리하여 분할 단계의 결과를 스케줄링하는 과정에 의해 진행되었다. 이러한 작업과정은 스케줄링 결과 스케줄이 불가능한 경우 시스템을 재설계 해야하는 문제점을 가진다. 본 논문에서는 분할 단계에서 스케줄링을 함께 고려하는 낮은 복잡도의 알고리즘을 제안한다. FDS를 응용한 기존 논문[4]이 고려하지 못한 자원제약에 의한 힘값 변이를 고려할 수 있도록 하였고 알고리즘 복잡도를 개선하기 위하여 종속성 제약 조건에 의해 받는 다른 노드의 힘값 계산 방법을 수정하였다. 수정된 계산 방법에서는 특정 노드와 경쟁 노드들의 제어구간별 상대적 스케줄 요구값의 크기에 의해 분할 대상 노드를 선택하게 된다. 제안된 논문의 실험결과는 시스템 제약시간을 만족하면서 구현비용을 저하시키고 알고리즘 실행시간 측면에서 효과적임을 보인다.

• ETRI Journal
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• v.25 no.6
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• pp.489-502
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• 2003

This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a cost-effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.477-485
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• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.267-276
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• 2021

The automotive industry and academic research have been continuously conducting research on standardization such as AUTOSAR (AUTomotive Open System ARchitecture) and ISO26262 to solve problems such as safety and efficiency caused by the complexity of electric/electronic architecture of automotive. AUTOSAR is an automotive standard software platform that has a layered structure independent of MCU (Micro Controller Unit) hardware, and improves product reliability through software modularity and reusability. And, ISO26262, an international standard for automotive functional safety and suggests a method to minimize errors in automotive ECU (Electronic Control Unit)s by defining the development process and results for the entire life cycle of automotive electrical/electronic systems. These design methods are variously applied in representative automotive safety-critical systems. However, since the functional and safety requirements are different according to the characteristics of the safety-critical system, it is essential to research the AUTOSAR functional safety design method specialized for each application domain. In this paper, a software functional safety mechanism design method using AUTOSAR is proposed, and a new failure management framework is proposed to ensure the high reliability of the product. The AUTOSAR functional safety mechanism consists of memory partitioning protection, timing monitoring protection, and end-to-end protection. The fault management framework is composed of several safety SWCs to maintain the minimum function and performance even if a fault occurs during the operation of a safety-critical system. Finally, the proposed method is applied to the Shift-by-Wire system design to prove the validity of the proposed method.