• Journal of Institute of Control, Robotics and Systems
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• v.19 no.2
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• pp.119-124
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• 2013

Recent increasing demand on the indoor localization requires more advanced and hybrid technology. This paper proposes an application of the hybrid indoor localization method based on a position-coded pattern that can be used with other existing indoor localization techniques such as vision, beacon, or landmark technique. To reduce the pattern-recognition error rate, the error detection and correction algorithm was applied based on Hamming code. The indoor localization experiments based on the proposed algorithm were performed by using a QCIF-grade CMOS sensor and a position-coded pattern with an area of $1.7{\times}1.7mm^2$. The experiments have shown that the position recognition error ratio was less than 0.9 % with 0.4 mm localization accuracy. The results suggest that the proposed method could be feasibly applied for the localization of the indoor mobile service robots.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.113-118
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• 2011

This paper has analyzed recognizing performance depending on the size of iris codes extracting by iris recognition algorithm using scale-space filtering. The iris images were created through pre-processing, the features were extracted by scale-space filtering, and the codes of 16 sizes were generated. The generated code's performance was compared for each code to calculate FAR and FRR by matching method utilizing Hamming distance. Every code had little overlapping portion between same person and other persons group so that the proposed algorithm's superiority was proved, and the performance of iris codes was analyzed for each size focused on convenience to use when implementing in realization. In addition, the iris codes suitable to iris recognition system that is high-reliable and is able to reduce user's inconvenience due to mis-rejection has been presented considering for commercialization.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.24-28
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• 1985

In this paper, the cyclic product codes which are capable of correcting random erros and burst errors simultaneously have been designed and constructed. First, the procedure for product of two cyclic codes is shown and thin the encoder and decoder system using the (7,4) cyclic Hamming code and the (3,1) cyclic code is implemented. The micro-computer is used for experiment and the system consists of encoder, decoder and interface circuits. The encoder of cyclic product code is implemented by interlacing encoders while the decoder is implemented by cascading decoders that interlace error trapping decoders. In conclusion, cyclic product codas are easily decodable and are capable of correcting four random errors and eight-burst errors. Better performance is obtained with low error rate.

• Journal of Communications and Networks
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• v.10 no.1
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• pp.5-9
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• 2008

Researchers have investigated many upper bound techniques applicable to error probabilities on the maximum likelihood (ML) decoding performance of turbo-like codes and low density parity check (LDPC) codes in recent years for a long codeword block size. This is because it is trivial for a short codeword block size. Previous research efforts, such as the simple bound technique [20] recently proposed, developed upper bounds for LDPC codes and turbo-like codes using ensemble codes or the uniformly interleaved assumption. This assumption bounds the performance averaged over all ensemble codes or all interleavers. Another previous research effort [21] obtained the upper bound of turbo-like code with a particular interleaver using a truncated union bound which requires information of the minimum Hamming distance and the number of codewords with the minimum Hamming distance. However, it gives the reliable bound only in the region of the error floor where the minimum Hamming distance is dominant, i.e., in the region of high signal-to-noise ratios. Therefore, currently an upper bound on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix cannot be calculated because of heavy complexity so that only average bounds for ensemble codes can be obtained using a uniform interleaver assumption. In this paper, we propose a new bound technique on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix using ML estimated weight distributions and we also show that the practical iterative decoding performance is approximately suboptimal in ML sense because the simulation performance of iterative decoding is worse than the proposed upper bound and no wonder, even worse than ML decoding performance. In order to show this point, we compare the simulation results with the proposed upper bound and previous bounds. The proposed bound technique is based on the simple bound with an approximate weight distribution including several exact smallest distance terms, not with the ensemble distribution or the uniform interleaver assumption. This technique also shows a tighter upper bound than any other previous bound techniques for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.111-121
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• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.2
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• pp.1-8
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• 1992

This paper is proposed a Modified WLD (Weighted Levenshtein Distance) algorithm for processor desihn of code-string matching. A proposed MWLD (Modified Weighted Levenshtein Distance) algorithm is consist of 1-dimension bit-serial array processor to pattern matching using a Hamming Distance. The proposed processor is applied to recognition of character with real time input. The recognition rate of Hangul strokes is resulted to 98.65$\%$

• Journal of the Korean Mathematical Society
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• v.46 no.5
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• pp.967-977
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• 2009

There are three standard weight functions on a linear code viz. Hamming weight, Lee weight, and Euclidean weight. Euclidean weight function is useful in connection with the lattice constructions [2] where the minimum norm of vectors in the lattice is related to the minimum Euclidean weight of the code. In this paper, we obtain an upper bound over the number of parity check digits for Euclidean weight codes detecting and correcting burst errors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of applied mathematics & informatics
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• v.26 no.1_2
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• pp.107-120
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• 2008

There has been a recent growth of interest in codes with respect to a newly defined non-Hamming metric grown as the Rosenbloom-Tsfasman metric (RT, or $\rho$, in short). In this paper, the definitions of the Lee complete $\rho$ weight enumerator and the exact complete $\rho$ weight enumerator of a code over $M_n_\times_s(Z_4)$ are given, and the MacWilliams identities with respect to this RT metric for the two weight enumerators of a linear code over $M_n_\times_s(Z_4)$ are proven too. At last, we also prove that the MacWilliams identities for the Lee and exact complete $\rho$ weight enumerators of a linear code over $M_n_\times_s(Z_4)$ are the generalizations of the MacWilliams identities for the Lee and complete weight enumerators of the corresponding code over $Z_4$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.180-186
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• 2013

The primary goal of attack on steganographic images, termed steganalysis, is to detect the presence of hidden data by finding statistical abnormality of a stego-media caused by data embedding. This paper proposes a novel steganographic scheme based on improving the (7, 4) Hamming code for digital images. The proposed scheme embeds a segment of six secret bits into a group of nine cover pixels at a time. The experimental results show that the proposed scheme achieves a 0.67bpp embedding payload and a slightly higher visual quality of stego images compared with the previous arts.