• Title/Summary/Keyword: HONoC

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A Latency Optimization Mapping Algorithm for Hybrid Optical Network-on-Chip (하이브리드 광학 네트워크-온-칩에서 지연 시간 최적화를 위한 매핑 알고리즘)

  • Lee, Jae Hun;Li, Chang Lin;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.131-139
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    • 2013
  • To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

Topology Design for Energy/Latency Optimized Application-specific Hybrid Optical Network-on-Chip (HONoC) (특정 용도 하이브리드 광학 네트워크-온-칩에서의 에너지/응답시간 최적화를 위한 토폴로지 설계 기법)

  • Cui, Di;Lee, Jae Hoon;Kim, Hyun Joong;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.83-93
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    • 2014
  • It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

The Reactivity and Regiochemical Effect of Nitrosonium Species in the Nitrosation of N-Methyl-N'-Substituted Phenylureas (N-메틸-N'-치환페닐우레아화합물들의 니트로소화 반응에 있어서 니트로소화 화학종의 반응성 및 위치화학적 영향)

  • Jack C. Kim;In-Seop Cho;Soon-Kyu Choi
    • Journal of the Korean Chemical Society
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    • v.35 no.3
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    • pp.240-248
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    • 1991
  • The regioselectivity in the nitrosation of seven N-methyl-N'-substituted phenylureas ($CH_3NHCONHC_6H_4-G$; G = H, p-CH$_3$, m-CH$_3$, m-CH$_3$O, p-F, m-F, m-Br) was examined using NaNO$_2$ and 4 different acids (diluted HCl, HCOOH, CH$_3$COOH, CF$_3$COOH). In all cases, the two regioisomeric products, N-nitroso-N-methyl-N'-substituted phenylureas (A) and N'-nitroso-N-methyl-N'-substituted phenylureas (B) were observed to be formed as major products and product ratios were determined by the integration of their methyl peaks in $^1$H-NMR. Electron donating substitutent(G) on phenyl of the ureas generally led to increase the ratio of B to A. The data have revealed that the relative sensitivity of the nitrosonium species (HONO, HCOONO, CH$_3$COONO, CF$_3$COONO) toward the change of electron density on nitrogen with phenyl substitutents are 1.00 : 0.93 : 0.78 : > ∼ 0.7.

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