• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.86-86
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• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.

• 공업화학
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• 제27권1호
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• pp.101-109
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• 2016

기존의 불산을 대체할 수 있는 평판디스플레이용 유리의 식각용액을 개발하고자 진행하였다. 본 연구과정을 통해 제안된 불산 대체 유리 식각용액은 산성불화암모늄 18~19 wt%, 황산 24~25 wt%, 물 45~46 wt%, 황산염 4~5 wt%, 규불화염 7~8 wt%로 구성되며, 사용된 식각용액의 재사용 시 보충용액으로서 해당조성의 식각용액을 전체의 5% 되게 보충함으로서 효과적으로 지속적으로 재사용이 가능하다. 개발된 식각용액은 $30^{\circ}C$에서 $5{\mu}m/min$ 이상의 식각속도를 나타내며, 반복 재사용 시에도 초기 식각액 전체 질량의 5% 추가로 보충함으로서 식각속도는 $0.1{\mu}m/min$ 이하로 편차로 식각속도가 안정적으로 유지되었다. 이 식각공정을 통해 얻어진 평판디스플레이용의 유리의 표면 상태는 Pin hole, Dimple 등이 발견되지 않는 양호한 품질을 나타내었다.

• 한국정밀공학회지
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• 제19권5호
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

• 대한치과보철학회지
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• 제33권4호
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• pp.693-704
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• 1995

This study was performed to evaluate effective surface conditioning method of In-Ceram core to improve bonding with resin cement. The surface of each sample was avraded with glass bead for 20 seconds and then subjected to one of the following conditions : no modification, sandblasting with $50{\mu}m$ slumimum oxide powders for 20 seconds, etching with 20% hydrofluoric acid for 5, 10, and 15 minutes(half of the etched samples were coated with silane), and sandblasting with $250{\mu}m$ aluminum oxide powders and silica coating whith Silicoater MD system(Kulzer, Germany). The surface morphology changes were examined with scanning electronic microscope(SEM. and the shear bond strength of In-Ceram core samples to resin cement(Panavis 21, Kurayay, Japan) were measured. It was concluded that : 1. By SEM observation, 20% HF acid etching did not create clear microretentive structure and surface roughness diminished with increace in etching time. Sandblasting was more effective than 20% hydrofluoric acid etching in producing microretentive structure. 2. The bond strengths of all In-Ceram core samples surface conditioned were increased that that of control group. 3. Silica coating showed higher bond strength than etching with 20% hydrofluoric acid. 4. The use of silane coating was more effective in improving bond strength than lengthening etching time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• 한국광학회:학술대회논문집
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• 한국광학회 2009년도 창립 20주년기념 특별학술발표회
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• pp.288-289
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• 2009

We report an optimum fabrication condition for formation of concave lens shaped core cross-section of silica single-mode fibers with hydrofluoric (HF) acid solutions and arc discharge. A desired depth of curved cross-section of the silica fiber core and its surface smoothness were obtained with optimized concentration of the HF solution, etching time, and arc discharge condition.

• 한국정밀공학회지
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• 제14권12호
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• pp.153-159
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• 1997

A thermally-driven polysilicon microactuator has been fabricated using surface micromachining techniques. It consists of P-doped polysilicon as a structural layer and TEOS(tetraethylorthosilicate) oxide as a sacrificial layer. The polysilicon was annealed for the relaxation of residual stress which is the main cause to its deformation such as bending and buckling. And newly developed HF GPE(gas-phase etching) process was also employed to eliminate the troublesome stiction problem using anhydrous HF gas and CH$_{3}$OH vapor, and successfully fabricated the microactuators. The actuation is incurred by the thermal expansion due to the current flow in the active polysilicon cantilever, which motion is amplified by lever mechanism. The moving distance of polysilicon microactuator was experimentally conformed as large as 21 .mu. m at the input voltage level of 10V and 50Hz square wave. The actuating characteris- tics are also compared with the simulalted results considering heat transfer and thermal expansion in the polysilicon layer. This microactuator technology can be utilized for the fabrication of MEMS (microelectromechanical system) such as microrelay, which requires large displacement or contact force but relatively slow response.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.20.2-20.2
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• 2009

최근 무전해 식각법을 이용한 실리콘 나노와이어 합성이 다양한 각도에서 이루어지고 있다. 무전해 식각법을 통한 나노와이어 합성은, 단결정 실리콘 기판에 촉매를 올려 기판을 식각할 수 있는데, 이 방법을 이용하여 넓은 면적의 수직방향으로 배열된 10 ~ 300nm 지름의 단결정 실리콘 나노와이어를 합성할 수 있다. 본 연구에서는 무전해 식각법으로 boron이 도핑된 p-type실리콘 기판을 식각하여 실리콘 나노와이어를 합성하였고, 단일 나노와이어의 field-effect transistor(FET) 소자가 가지는 전기적 특성에 대하여 분석하였다. 특히 무전해 식각법을 이용하여 나노와이어를 합성할 때, 촉매로 사용되는 Ag particle이 나노와이어에 미치는 영향에 대해서 분석해 보았다. FET 소자의 게이트 절연막은 가장 일반적으로 사용되는 SiO2 (300nm)와 고유전체로 잘 알려진HfO2(80nm)를 사용하여 전기적 특성을 비교하여 보았다. 한편, HfO2 박막은 atomiclayer deposition(ALD)장비를 이용하여 증착하였다. 합성된 실리콘 나노와이어의 경우 X-ray diffraction(XRD)로 결정성을 확인하였으며, high-resolution transmission electron microscopy(HRTEM)으로 결정성 및 나노와이어의 표면 형태를 확인하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, subthreshold voltage값을 평가하였다.

• 한국표면공학회지
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• 제55권5호
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• pp.247-260
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• 2022

Since the first report on ferroelectricity in Si-doped hafnia (HfO2), this emerging ferroelectrics have been considered promising for the next-generation semiconductor devices with their characteristic nonvolatile data storage. The robust ferroelectricity in the sub-10-nm thickness regime has been proven by numerous research groups. However, extending their scalability below the 5 nm thickness with low temperature processes compatible with the back-end-of-line technology. In this review, therefore, the current status, technical issues, and their potential solutions of atomic layer deposition (ALD) of HfO₂-based ferroelectrics are comprehensively reviewed. Several technical issues in the physical scaling of the ferroelectric thin films and potential solutions including advanced ALD techniques including discrete feeding ALD, atomic layer etching, and area selective ALD are introduced.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3310-3312
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• 1999

We have studied the method of silicon direct bonding using the mixture of $HNO_$, $H_2O_2$, and HF chemicals called the controlled slight etch (CSE) solution for the effective wafer cleaning. CSE, two combinations of oxidizing and etching agents, have been used to clean the silicon surfaces prior to wafer bonding. Two wafers of silicon and silicon dioxide were contacted each other at room temperature and postannealed at $300{\sim}1100^{\circ}C$ in $N_2$ ambient for 2.5 h. We have cleaned silicon wafers with the various HF concentrations and characterized the parameters with regard to surface roughness, chemical nature, chemical oxide thickness, and bonding energy. It was observed that the chemical oxide thickness on silicon wafer decreased with increasing HF concentrations. The initial interfacial energy and final energy postannealed at $1100^{\circ}C$ for 2.5h measured by the crack propagation method was 122 $mJ/m^2$ and 2.96 $mJ/m^2$, respectively.