• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1018-1025
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• 2011

Scalable Video Coding (SVC) extension of H.264/AVC is a new video coding standard for media convergence by providing diverse videos of different spatial-temporal-quality layers with a single bitstream. Recently, real-time SVC codecs are being developed for the application areas of surveillance video and mobile video, etc. This paper presents the design and implementation of a H.264/SVC decoder based on an embedded DSP using Open SVC Decoder (OSD) which is a real-time software decoder designed for the PC environment. The implementation consists of porting C code of the OSD software from PC to DSP environment, profiling the complexity performance of OSD with further optimization, and integrating the optimized decoder into the TI Davinci EVM (Evaluation Module). 50 QCIF/CIF frames or 15 SD frames per second can be decoded with the implemented DSP-based SVC decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.805-812
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• 2008

H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

• ETRI Journal
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• v.27 no.5
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• pp.491-496
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• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.162-164
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• 2010

H.264/AVC(Advanced Video Coding) is a standard for video compression. H.264/AVC provides good video quality at substantially lower bit rates than previous standards. In this papers, we propose the efficient architecture of H.264/AVC decoder using GPGPU. GPGPU can process many of operation in parallel. IQ/IDCT is possible that parallel processing in H.264/AVC decoding algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2020-2025
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• 2006

H.264/AVC is newest video coding standard of the ITU-T Video coding Experts Group and the ISO/IEC Moving Picture Expets Group. Recently H.264/AVC has been adopted as a video compression standard in DMB and multimedia equipments. In this paper, we propose a H.264/AVC intra frame decoder which can minimize the memory usage and chip size. The proposed intra frame decoder is described in VHDL language and simulated in model_sim. It was verified in chip level by downloading to XCV1000E FPGA chip.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.350-353
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• 2007

This paper presents an real-time implementation of H.264/AVC High 4:4:4 Predictive profile decoder using general-purpose processors by exploiting multi-threading technique and Single Instruction Multiple Data (SIMD) instructions without any quality degradation. We analyze differences between the existing High profile and High 4:4:4 Predictive profile decoder, and show various optimization techniques to decode high fidelity and high definition (HD) video in real-time. Simulation results show that the proposed decoder can play high fidelity HD video at average 40 frames per seconds (fps) for the IBBrBP bistream and about 50 fps for the Intra-only bitstream.

• ETRI Journal
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• v.28 no.4
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.409-410
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• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.801-808
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• 2007

Video coding standards such as MPEG-2, MPEG-4, H.263, and H.264 transmit a compressed video data using wired/wireless communication line with limited bandwidth. Because highly compressed bit-streams is likely to fragile to error from channel noise, video is damaged by error. There have been many research works on error concealment techniques, which recover transmission errors at decoder side [1, 2]. We designed an error concealment technique for lost motion vectors of H.264 video coding. In this paper, we propose a Kalman filter based motion vector recovery scheme, and experimented with standard video sequences. The experimental results show that our scheme restores original motion vector with more precision of 0.91 - 1.12 on average over conventional H.264 decoding with no error recovery.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.62-68
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• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.