• The Journal of the Korea Contents Association
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• v.9 no.2
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• pp.27-35
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• 2009

In this paper, we present result of embedded system based H.264/SVC decoder circuit design and system implementation. To deal with the standardized H.264/SVC functionalities, the presented SVC decoder system is consist of hardware engine design and software with ARM core processor. In order to improve the feasibility and applicability, and reduce the decoder complexity, the implemented system is constructed with only the consideration of IPPP structure scalability without using the full B-picture architecture. Finally, we will show the decoding image result using the designed H.264/SVC decoder system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.409-410
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• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.108-123
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• 2007

As H.264/AVC standard has proven to be a key technology of multimedia application, many researches to improve H.264/AVC standard are actively conducted. Those researches are conducted in various ways such as algorithm analysis and improvement or structure enhancement for reducing bottlenecks of performance. Even though targets and directions of those studies are not the same, performance of H.264/AVC standard is commonly analyzed in the early phase. In analysis phase, potential problems with H.264/AVC standard are identified and the most critical problem which has serious effects on performance is determined. Therefore, analysis phase is one of the important steps to decide overall directions and targets of the research. This research proposes a mathematical model which can be used in the early performance analysis phase to estimate performance in conducting research of improving the performance of H.264/AVC Baseline Profile decoder. The proposed model is designed by considering many variables of H.264/AVC decoder operation so that it is easy to predict its performance according to changes in each element.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.805-812
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• 2008

H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

• ETRI Journal
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• v.27 no.5
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• pp.491-496
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• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.62-68
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• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1018-1025
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• 2011

Scalable Video Coding (SVC) extension of H.264/AVC is a new video coding standard for media convergence by providing diverse videos of different spatial-temporal-quality layers with a single bitstream. Recently, real-time SVC codecs are being developed for the application areas of surveillance video and mobile video, etc. This paper presents the design and implementation of a H.264/SVC decoder based on an embedded DSP using Open SVC Decoder (OSD) which is a real-time software decoder designed for the PC environment. The implementation consists of porting C code of the OSD software from PC to DSP environment, profiling the complexity performance of OSD with further optimization, and integrating the optimized decoder into the TI Davinci EVM (Evaluation Module). 50 QCIF/CIF frames or 15 SD frames per second can be decoded with the implemented DSP-based SVC decoder.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1046-1050
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• 2005

영상 정보의 발전으로 다양한 멀티미디어 서비스를 가능하게 하였고 네트워크와 IT의 발전으로 사용자가 풍부한 정보를 접할 수 있는 기회를 제공하였다. 이러한 동영상과 정지영상의 많은 정보를 압축하는 여러 방식 중에서 디지털 비디오 압축 관련 국제 표준안 중 MPEG-4와 H.264가 발표되었다. 유연성이 좋은 MPEG-4와 달리 H.264는 비디오 프레임의 효율적인 압축과 신뢰성을 강조 한다. 특히 H.264의 압축 기술은 HDTV처럼 큰 영상 뿐 아니라 카메라폰이나 DMB등의 특히 작은 크기의 영상에서 고품질의 영상을 보다 효율적으로 제공 한다. 본 논문은 기존의 동영상 압축 표준에 비하여 높은 압축성능과 유연성의 장점을 가지고 있고 표준 H.264/AVC에서 공간적 예측을 사용하여 비디오 프레임을 압축하는 방법인 Intra coding 에서 사용하는 여러 모드 중 4*4 예측모드를 연구하여 C언어를 이용한 최적화된 시뮬레이션과 Intra coding decoder의 성능평가를 통한 최적화를 실시하였고, 최적화된 예측 정보를 바탕으로 Intra coding decoder를 VHDL언어를 이용하여 하드웨어로 구현하였다.

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.