• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.175-178
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• 2009

H.264/AVC is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. In this paper, we explained Intra Prediction in H.264/AVC, which is able to achieve higher compressing efficiency from correlation removal of adjacent samples in spatial domain, and proposed efficient Intra Predictor architecture design for H.264/AVC decoder. The proposed system reduced computation cycle using processing element and precomputation processing element and also reduced the number of access to external memory using efficient register. We designed the proposed system with Verilog-HDL and verified with suitable test vector. The proposed Intra Predictor achieved about 60% cycle reduction comparing with existing Intra Predictors.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.91-94
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• 2003

H.264/AVC is the upcoming video coding standard of ITU-T H.264 and ISO MPEG-4 AVC. The new standard can achieve a significant improvement up to 50％ in compression ratio compared to MPEG-4 advanced simple profile. In this paper, we propose the novel intra prediction scheme to speed up intra prediction process in H.264/AVC decoder and show the hardware architecture for it. The proposed scheme uses the concurrent processing of the 4$\times$4 intra prediction, which is based on that some 4$\times$4 block pairs in a 16$\times$16 luma block can be processed concurrently. The proposed scheme can reduce intra prediction time by 33 ％.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

• Journal of IKEEE
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• v.14 no.2
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• pp.76-81
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• 2010

The need for dedicated hardware continue to decrease as the mobile CPU's performance increases. But, there is a limit to a mobile CPU's performance. GP-GPU(General-Purpose computing on Graphics Processing Units) can improve performance without adding other dedicated hardware. This paper presents the implementation of Inverse Quantization, Inverse DCT and Color Space Conversion module in H.264/AVC decoder using GP-GPU for a mobile environments. The proposed architecture improves approximately 40% of performance when it use all the features.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.723-726
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• 2008

H.264/AVC는 다양한 블록 사이즈에 따라 움직임 보상을 수행한다. 본 논문은 1/4정밀도 화소를 지원하는 효율적인 움직임 보상에 대해 연구하였다. 참조 프레임의 데이터로 사용하기 위한 메모리의 접근을 줄이고 2개의 6-tap 필터를 사용하는 움직임 보상을 제안한다. 소프트웨어 검증을 통한 최적화 된 알고리즘을 사용하여 하드웨어 설계 언어를 이용하여 기술하고 ModeSim 6.0a를 이용한 데이터 검증을 수행하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.349-354
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• 2009

In this paper, a new motion compensation scheme to reduce external memory access frequency which is one of the major bottlenecks for real-time decoding is proposed. Most H.264/AVC decoders store reference pictures in external memories due to the large size and reference blocks are read into the decoder core as needed during decoding. If the reference data access is done for each reference block in decoding sequence, the memory bandwidth can be unacceptable for real-time decoding. This paper presents a memory access scheme for motion compensation to read as many reference data as possible with reduced memory access frequency by analyzing reference data access pattern for each macroblock. Experimental results show that the proposed motion compensation scheme leads to approximately 30% improvement in memory bandwidth requirement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.102-116
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• 2009

There have been lots of researches for H.264/AVC performance enhancement on a multi-core processor. The enhancement has been performed through parallelization methods. Parallelization methods can be classified into a task-level parallelization method and a data level parallelization method. A task-level parallelization method for H.264/AVC decoder is implemented by dividing H.264/AVC decoder algorithms into pipeline stages. However, it is not suitable for complex and large bitstreams due to poor load-balancing. Considering load-balancing and performance scalability, we propose a horizontal data level parallelization method for H.264/AVC decoder in such a way that threads are assigned to macroblock lines. We develop a mathematical performance expectation model for the proposed parallelization methods. For evaluation of the mathematical performance expectation, we measured the performance with JM 13.2 reference software on ARM11 MPCore Evaluation Board. The cycle-accurate measurement with SoCDesigner Co-verification Environment showed that expected performance and performance scalability of the proposed parallelization method was accurate in relatively high level

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.23-30
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• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06d
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• pp.325-327
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• 2006

H.264/AVC는 ITU-T H.264와 ISO/IEC 14496-10(MPEG-4 Part 10)으로 승인된 새로운 국제 비디오 압축 표준이다. H.264/AVC는 압축부호화 효율(이하 압축률)이 높으며 MPEG-2나 MPEG-4등에 비해 압축률이 2배 이상 향상되었으나 복잡도 또한 훨씬 증가하였다. 월등한 압축성능 때문에 방송 분야(DTV 등), 저장용 시스템 분야(PVR 등)에 많은 응용 분야들에 적용하기 위한 움직임이 있다. 그러나, 디코더로 구현하면 복잡도 증가하는 문제가 발생한다. HD급을 지원하기 위한 메모리 대역폭의 경우 MPEG-2 HD에 비해 H.264/AVC만의 복잡한 움직임 보상으로 인해 2배 이상이 요구된다. H.264/AVC 디코더는 두 개의 참조픽처를 이용하여 움직임 보상하는 B-픽처와 쌍예측 픽처가있다. 여기서, 참조픽처를 각각 하나씩만 사용하여 디코딩 하면 기존의 복잡도를 줄일 수 있다. 본 논문에서 제안하는 방법은 하나의 참조픽처 선택으로 H.264/AVC 소프트웨어 디코더에서 움직임 보상을 한다. 이로 인하여 복잡도와 메모리 대역폭이 감소하는 방법을 제안한다.