• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.582-590
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• 2010

he rate-distortion optimization (RDO) method in the H.264/AVC encoder is a technology that improves the coding efficiency, but increases the computational complexity. In this paper, a fast Intra mode decision algorithm using DCT (Discrete Cosine Transform) coefficients distribution is proposed to reduce the H.264 encoder complexity. The proposed method reduces the encoder complexity on average 68.40%, while the coding efficiency is slightly decreased compared with the H.264/AVC encoder.

• Journal of the Semiconductor & Display Technology
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• v.14 no.1
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• pp.51-53
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• 2015

H.264/AVC is international video coding standard, which shows improved code and efficiency than the existing video standards. H.264/AVC proposes data partitioning method that considerably to be an effective layering technique which separates important addressing data from the residual data. UEP(Unequal Error Protection) turbo code of H.264/AVC uses retransmission system to get the UEP effectively. However, Data partitioning system of H.264/AVC is inefficient method in turbo code of H.264/AVC. Based on this observation, we propose the new UEP turbo code algorithm that reconstructs input sequence of turbo code without retransmission system.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.687-690
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• 2005

H.264/AVC에서 압축 효율을 향상시키기 위해 사용된 entropy coding중에 CABAC(Context-based Adaptive Binary Arithmetic Coding)은 하드웨어 복잡도가 높고 bit-serial 과정에서 data dependancy가 존재하기 때문에 빠른 연산이 어렵다. 본 논문에서는 adaptive arithmetic encoder와 정규화 과정을 효율적으로 구성하여 각 입력 심벌이 정규화 과정의 반복횟수에 관계없이 고정된 cycle에 encoding이 되도록 하였다. 제안한 구조는 pipeline으로 구성하기 용이하며, 이 경우 매 cycle에 한 입력 심벌의 encoding이 가능하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1485-1490
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• 2005

Variable length code is an integral component of many international standards on image and video compression currently. Context-based Adaptive Variable Length Coding(CAVLC) is adopted by the emerging JVT(also called H.264, and AVC in MPEG-4). In this paper, we design an architecture for CAVLC encoder, including a coeff_token encoder, level encoder, total_zeros encoder and run_before encoder. The designed CAVLC encoder can encode one syntax element in one clock cycle. As a result of implementation by Vertex-1000e of Xilinx, its operation frequency is 68MHz. Therefore, it is very suitable for video applications that require high throughput.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Journal of Internet Computing and Services
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• v.11 no.2
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• pp.49-60
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• 2010

H.264/AVC offers a better encoding efficiency than conventional video standards by adopting many new encoding techniques. However, the advanced coding techniques also add to the overall complexity for H.264/AVC encoder. Accordingly, it is necessary to perform optimization to alleviate the level of complexity for the video encoder. The amount of computation for motion estimation is of particular importance. In this paper, we propose a diamond web-grid search algorithm combined with efficient stationary block skip method which employs full diamond and dodecagon search patterns, and the variable thresholds are used for performing an effective skip of stationary blocks. The experimental results indicate that the proposed technique reduces the computations of the unsymmetrical-cross multi-hexagon-grid search algorithm by up to 12% while maintaining a similar PSNR performance.

• Journal of Broadcast Engineering
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• v.17 no.3
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• pp.471-479
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• 2012

Intra prediction is one of the significant techniques in H.264/AVC reference software; however, it has heavy computational complexity. In order to solve this problem, many fast algorithms have been proposed. In this paper, we propose a fast intra mode decision algorithm which predicts the edge direction of the current block using sub-sampled pixels to reduce high computational complexity of the H.264/AVC encoder. The proposed algorithm shows that it not only improves the coding performance but also reduces the computational complexity of the H.264/AVC encoder compared to previous algorithms. The experimental results show that the proposed algorithm achieves the encoding time reduction of 75.93% on an average with slight peak signal-to-noise ratio (PSNR) drop and bit-rate increment.