• The Journal of the Korea Contents Association
• /
• v.13 no.6
• /
• pp.20-29
• /
• 2013

The compression of video data is intended for real-time transmission of band-limited channels. Compressed video bit-streams are very sensitive to transmission error. If we lose packets or receive them with errors during transmission, not only the current frame will be corrupted, but also the error will propagate to succeeding frames due to the spatio-temporal predictive coding structure of sequences. Error detection and concealment is a good approach to reduce the bad influence on the reconstructed visual quality. To increase concealment efficiency, we need to get some more accurate error detection algorithm. In this paper, We hide specific data into the motion vector difference of each macro-block, which is obtained from the procedure of inter prediction mode in H.264/AVC. Then, the location of errors can be detected easily by checking transmitted specific data in decoder. We verified that the proposed algorithm generates good performances in PSNR and subjective visual quality through the computer simulation by H.324M mobile simulation tool.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.45 no.2
• /
• pp.26-32
• /
• 2008

Video compression schemes have been developed and used for many years. Currently, H.264/AVC is the most efficient video coding standard. The H.264/AVC baseline profile adopts CAVLC(Context-Adaptive Variable Length Coding) method as an entropy coding method. CAVLC gives better performance in compression ratios than conventional VLC(Variable Length Coding). However, because CAVLC decoder uses a lot of VLC tables, the CAVLC decoder requires a lot of area in terms of hardware. Conversely, since it must look up the VLC tables, it gives a worse performance in terms of software. In this paper, we propose a new hierarchical grouping method for the VLC tables. We can obtain an index of codes in the reconstructed VLC tables by simple arithmetic operations. In this method, the VLC tables are accessed just once in decoding a symbol. We modeled the proposed algorithm in C language, compiled under ARM ADS1.2 and simulated it with Armulator. Experimental results show that the proposed algorithm reduces execution time by about 80% and 15% compared with the H.264/AVC reference program JM(Joint Model) 10.2 and the arithmetic operation algorithm which is recently proposed, respectively.

• Journal of Broadcast Engineering
• /
• v.16 no.6
• /
• pp.1018-1025
• /
• 2011

Scalable Video Coding (SVC) extension of H.264/AVC is a new video coding standard for media convergence by providing diverse videos of different spatial-temporal-quality layers with a single bitstream. Recently, real-time SVC codecs are being developed for the application areas of surveillance video and mobile video, etc. This paper presents the design and implementation of a H.264/SVC decoder based on an embedded DSP using Open SVC Decoder (OSD) which is a real-time software decoder designed for the PC environment. The implementation consists of porting C code of the OSD software from PC to DSP environment, profiling the complexity performance of OSD with further optimization, and integrating the optimized decoder into the TI Davinci EVM (Evaluation Module). 50 QCIF/CIF frames or 15 SD frames per second can be decoded with the implemented DSP-based SVC decoder.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.6
• /
• pp.30-35
• /
• 2007

H.264/AVC provides better quality than other algorithms by using a deblocking filter to remove blocking distortion on block boundary of the decoded picture. However, this filtering process includes lots of memory accesses, which cause delay of overall decoding time. In this paper, we propose a data-reuse algorithm to speed up the process for the deblocking filter. To reuse the data, a new filtering order is suggested. By using this order, we reduce the memory access and accelerate the deblocking filter. The modeling of proposed algorithm is compiled under ARM ADS1.2 and simulated with Armulator. The results of the experiment compared with H.264/AVC standard are achieved on average 58.45% and 57.93% performance improvements at execution cycles and memory access cycles, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.06a
• /
• pp.510-513
• /
• 2007

가변길이 부호는 많은 이미지 및 영상 표준에서 폭넓게 사용되는 기법이다. 특히 국제 표준인 JVT와 중국 A/V 표준인 AVS는 엔트로피 코딩을 수행하기 위해 Exp-Golomb 코드에 기반한 UVLC(Universal Variable Length Code)를 채용하고 있다. 본 논문에서는 H.264/AVC의 엔트로피 코딩에서 사용되는 Exp-Golomb CODEC의 하드웨어 구현에 대해 연구하였다. 식의 간략화로 구현하기 어려운 log함수와 거듭제곱 연산을 하지 않으며, 첫 번째 1 검출기와 누산기 제어에 의한 배럴 쉬프터를 통하여 별도의 시간 지연 없이 부호화 및 복호화가 되도록 설계하였다. Xilinx ISE툴을 사용하여 합성하고, 보드 수준에서 PCI인터페이스를 사용하여 검증하였다. 본 논문에서 설계된 Exp-Glomb CODEC은 H.264/AVC 및 AVS와 같은 분야에서 응용이 가능할 것으로 예견된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.444-447
• /
• 2011

In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.12
• /
• pp.50-57
• /
• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• The Journal of the Korea Contents Association
• /
• v.8 no.5
• /
• pp.29-37
• /
• 2008

To transmit video bit stream over low bandwidth such as wireless channel, high compression algorithm like H.264 codec is exploited. In transmitting high compressed video bit-stream over low bandwidth, packet loss causes severe degradation in image quality. In this paper, a new algorithm for recovery of missing or erroneous motion vector is proposed. Considering that the missing or erroneous motion vectors in blocks are closely correlated with those of neighboring blocks. Motion vector of neighboring blocks are clustered according to average linkage algorithm clustering and a representative value for each cluster is determined to obtain the candidate motion vector sets. As a result, simulation results show that the proposed method dramatically improves processing time compared to existing H.264/AVC. Also the proposed method is similar to existing H.264/AVC in terms of visual quality.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.20-27
• /
• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.44 no.4 s.316
• /
• pp.8-16
• /
• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of K264/AVC standard encoder is greatly increased. Specifically, the inter/intra mode decision method using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision. In the proposed method, we reduce the complexity of the $4{\times}4$ mode decision process using $4{\times}4$ simple square filters, and using spatial block correlation method. Additionally, exploiting the best mode of sub_macroblock in $Inter8{\times}8$ mode, we proposed an algorithm to eliminate some intra modes in current macroblock mode decision process. In addition, we employed a method to raise the probability to select SKIP, $Intra16{\times}16$, and $Intra16{\times}16$ modes which usually show low complexity and low bitrate compared with other modes. From the simulation results, the proposed algorithm reduce the encoding time by maximum 83% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.