• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.42-49
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• 2011

In this paper, we propose a fast macroblock mode decision algorithm in H.264/AVC, based on the image sequence statistics. Specically, considering the directional characteristics of image sequences, we eliminate sub$8{\times}4$ or sub$4{\times}8$ mode decision process based on the rate-distortion cost of Inter$16{\times}8$ or Inter$8{\times}16$ mode respectively. Additionally, exploiting the optimal modes of submacroblock in inter$8{\times}8$ mode, we propose an algorithm to eliminate Intra$4{\times}4$ or Intra$16{\times}16$ mode decision process selectively. From the simulation results, the proposed method reduce the encoding time by maximum 70% of total, compared with the other conventional methods.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.6
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• pp.30-35
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• 2007

H.264/AVC provides better quality than other algorithms by using a deblocking filter to remove blocking distortion on block boundary of the decoded picture. However, this filtering process includes lots of memory accesses, which cause delay of overall decoding time. In this paper, we propose a data-reuse algorithm to speed up the process for the deblocking filter. To reuse the data, a new filtering order is suggested. By using this order, we reduce the memory access and accelerate the deblocking filter. The modeling of proposed algorithm is compiled under ARM ADS1.2 and simulated with Armulator. The results of the experiment compared with H.264/AVC standard are achieved on average 58.45% and 57.93% performance improvements at execution cycles and memory access cycles, respectively.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.793-796
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• 2011

H.264/AVC compresses video data by applying DCT transform, quantization and entropy coding processes to the residual signal obtained by inter/intra prediction. This paper proposes a method enhancing an existing DC offset adjustment technology which uses information of neighboring blocks to reduce residual information for improving coding efficiency. DC offset information is not sent over bitstreams, but calculated in the same way both in the decoder and in the encoder. Experimental results show that the proposed method enhances coding efficiency by 0.25% in average BD-Rate compared to H.264/AVC and gives better or worse coding efficiency compared to the existing DC offset method depending on video sequences with coding efficiency degradation by 0.09% in average BD-Rate. This experimental results also show that further coding efficiency improvement is possible by applying the proposed method adaptively to slice or macroblock coding units.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.73-83
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• 2007

In this paper, we propose macroblock(MB)-based adaptive interpolation filter method for improving coding efficiency in H.264/AVC. In the proposed method, nine separable two-dimensional(2D) interpolation filters are applied for precisely compensating motions in various directions. The optimal cost function which considers the bit rate and distortion for coding the MB is defined. The filter is adaptively selected per MB for minimizing the defined cost function. In the experimental results, the proposed method shows more excellent in coding efficiency than the conventional methods for the various standard $QCIF(176{\times}144)/CIF(352{\times}288)$ video test sequences. It leads to about 6.25%(1 reference frame) and 3.46%(5 reference frames) bit rate reduction on average compared to the H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.1
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• pp.64-74
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• 2008

It is well-known that the coding efficiency of CABAC which is one of the entropy coding methods in H.264/AVC is lower than that of CAVLC at high bitrate in intra coding, even if CABAC shows higher coding efficiency than CAVLC. Therefore, for high quality video application, this paper proposes new binarization methods about the quantized DCT coefficients that are partitioned into four regions such that CABAC shows similar coding efficiency to CAVLC at high bitrate. The proposed binarization methods consist of separate binarization tables about the four partitioned DCT coefficients considering the statistical characteristics of the quantized DCT coefficients. The proposed binarizaton method for the quantized DCT coefficients shows higher coding efficiency than CABAC in H.264/AVC and shows very similar result to CAVLC at high bitrate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.312-320
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• 2008

The macroblock-based adaptive interpolation filter method has been considered to be able to achieve high coding efficiency in H.264/AVC. In this method, although the filter selection criterion considered in terms of rate and distortion have showed a good performance, it still leaves room for improvement. To improve high coding efficiency better than conventional method, we propose a new filter selection criterion which considers two bit rates, motion vector and prediction error, and reconstruction error. In addition, the algorithm for reducing the overhead of transmitting the selected filter information is presented. Experimental results show that the proposed method significantly improves the coding efficiency compared to ones using conventional criterion. It leads to about a 5.19% (1 reference frame) and 5.14% (5 reference frames) bit rate savings on average compared to H.264/AVC, respectively.

• Journal of Broadcast Engineering
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• v.13 no.1
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• pp.137-151
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• 2008

H.264/AVC is showed high coding efficiency more than previous video coding standard by using new coding tools. Specially, Variable block-based motion estimation and Rate-Distortion Optimization are very important coding tools in H.264/AVC. These coding tools have high coding efficiency, however the encoder complexity greatly increase due to these coding tools. In this paper, we propose early SKIP mode decision and selective inter/intra mode decision to reduce the computational complexity. Simulation results show that the proposed method could reduce encoding time of the overall sequences by 30% on average than JM 10.2 without noticeable degradation of coding efficiency. Besides, the proposed method runs over twice as fast as the previous proposed Fast Coding Mode Selection method (FCMS)[5].