• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1572-1575
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• 2005

Poly(vinyl phenol)(PVP)/$TiO_2$ nanocomposite the films have been prepared incorporating metal alkoxide with vinyl polymer to obtain high dielectric constant gate insulating material for a organic thin film transistor. The surface composition, the morphology, and the thermal and electrical properties of the hybrid nanocomposite films were observed by ESCA, scanning electron microscopy (SEM), atomic force microscopy(AFM), and thermogravimetric analysis (TGA). Thin hybrid films exhibit much higher dielectric constants (7.79 at 40wt% metal alkoxide).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.45-48
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• 2002

Poly(3-hexylthiophene) or P3HT based organic thin film transistor (OTFT) array was fabricated on flexible poly carbonate substrates and the electrical characteristics were investigated. As the gate dielectric, a dual layer structure of polyimide-$SiO_2$ was used to improve the roughness of $SiO_2$ surface and further enhancing the device performance and also source-drain electrodes were $O_2$ plasma treated for improvement of the electrical properties, such as drain current and field effect mobility. For the active layer, polymer semiconductor, P3HT layer was printed by contact-printing and spin-coating method. The electrical properties of OTFT devices printed by both methods were evaluated for the comparison. Based on the experiments, P3HT-based OTFT array with field effect mobility of 0.02~0.025 $cm^{2}/V{\cdot}s$ and current modulation (or $I_{on}/I_{off}$ ratio) of $10^{3}\sim10^{4}$ was fabricated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.821-829
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• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.

• Structural Engineering and Mechanics
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• v.51 no.3
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• pp.471-485
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• 2014

Until now, the finite corner stiffness of the right-angle frames used as horizontal girders in a bonnet, have not been considered during the design process to result in not a precise result. This paper presents a design equation set for right-angle frames used as horizontal girders in a bonnet assuming rigid corner stiffness. By comparing the center stresses of the right-angle frame according to the design equation set with the results of the finite element method, the master curves for the empirical corner stiffness can be determined as a function of slenderness ratio. A second design equation set for a right-angle frame assuming finite corner stiffness was derived and compared with the first equation set. The master curves for the corner stiffness and the second design equation set can be used to determine the design moments at the centers of the girder so that the bending stresses can be analyzed more precisely.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.99-99
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• 2010

Recently, amorphous transparent oxide semiconductors (TOS) have been widely studied for many optoelectronic devices such as AM-OLED (active-matrix organic light emitting diodes). The TOS TFTs using a-IGZO channel layers exhibit a high electron mobility, a smooth surface, a uniform deposition at a large area, a high optical transparency, a low-temperature fabrication. In spite of many advantages of the sputtering process such as better step coverage, good uniformity over large area, small shadow effect and good adhesion, there are not enough researches about characteristics of a-IGZO thin films. In this study, therefore, we focused on the electrical properties of a-IGZO thin films as a channel layer of TFTs. TFTs with the a-IGZO channel layers and Y2O3 gate insulators were fabricated. Source and drain layers were deposited using ITO target. TFTs were deposited on unheated non-alkali glass substrates ($5cm{\times}5cm$) with a sintered ceramic IGZO disc (3 inch $\varnothing$, 5mm t), Y2O3 disc (3 inch $\varnothing$, 5mm t) and ITO disc (3 inch $\varnothing$, 5mm t) as a target by magnetron sputtering method. The O2 gas was used as the reactive gas. Deposition was carried out under various sputtering conditions to investigate the effect of sputtering process on the characteristics of a-IGZO thin films. Correlation between sputtering factors and electronic properties of the film will be discussed in detail.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.211.1-211.1
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• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.452-455
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• 2003

[ $ZrO_2$ ] dielectric layers were grown on the p-type Si (100) substrate by metalorganic molecular beam epitaxy(MOMBE). Zrconium t-butoxide, $Zr(O{\cdot}t-C_4H_9)_4$ was used as a Zr precursor and Argon gas was used as a carrier gas. The thickness of the layers was measured by scanning electron microscopy (SEM) and the properties of the $ZrO_2$ layers were evaluated by X-ray diffraction, high frequency capacitance-voltage measurement. and HF C-V measurements have shown that $ZrO_2$ layer grown by MOMBE has a high dielectric constant (k=18-19). The growth rate is affected by various process variables such as substrate temperature, bubbler temperature, Ar, and $O_2$ gas flows.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.230-233
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• 2001

FeSi2/Si Layer were grown using FeSi2, Si wafer by the chemical transport reactio nmethod. The directoptical energy gap was found to be 0.871eV at 300 K. The Hall effect is a physical effect arising in matter carrying electric current inthe presence of a magnetic field. The effect is named after the American physicist E. H. Hall, who discovered it in 1879. IN this paper, we study electrical properties of FeSi2/Si layer. And then we measured Hall coefficient Hall mobility, carrier density and Hall voltage according to variation magnetic field and temperature, Because of important part for it applicationVarious phase of silicide is formed at the metal-Si interface when transition metal contacts to Si. Silicides belong to metallic or semiconducting according to their electrical and optical properties. Metallic silicides are used as gate electrodes or interconnections in VLSI devices. Semiconducting silicides can be used as a new material for IR detectors because of their narrow energy band gap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.234-237
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• 2001

FeSi2/Si Layer were grown using FeSi2, Si wafer by the chemical transport reactio nmethod. The directoptical energy gap was found to be 0.871eV at 300 K. The Hall effect is a physical effect arising in matter carrying electric current inthe presence of a magnetic field. The effect is named after the American physicist E. H. Hall, who discovered it in 1879. IN this paper, we study electrical properties of FeSi2/Si layer. And then we measured Hall coefficient Hall mobility,carrier density and Hall voltage according to variation magnetic field and temperature, Because of important part for it applicationVarious phase of silicide is formed at the metal-Si interface when transition metal contacts to Si. Silicides belong to metallic or semiconducting according to their electrical and optical properties. Metallic silicides are used as gate electrodes or interconnections in VLSI devices. Semiconducting silicides can be used as a new material for IR detectors because of their narrow energy band gap.