• 제목/요약/키워드: Gummel Number

검색결과 5건 처리시간 0.026초

직접회로용 BJT의 베이스 Gummel Number 해석 방법에 관한 연구 (A Study on the Method of the Analysis of the Base Gummel Number of the BJT for Integrated Circuits)

  • 이은구;김철성
    • 대한전기학회논문지:전기물성ㆍ응용부문C
    • /
    • 제52권2호
    • /
    • pp.74-79
    • /
    • 2003
  • The method of the analysis of the base Gummel number of the BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of NPN BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data and the transistor saturation current of PNP BJT shows an averaged relative error of 9.2% compared with the measured data

집적회로용 PNP BJT의 베이스 Gummel Number 계산 방법에 관한 연구 (A study on the method of the calculation of the base Gummel number of the PNP BJT for integrated circuits)

  • 이은구;이동렬;김태한;김철성
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
    • /
    • pp.141-144
    • /
    • 2002
  • The method of the analysis of the base Gummel number of the PNP BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of PNP BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data.

  • PDF

베이스 영역의 불순물 분포를 고려한 집적회로용 BJT의 역포화전류 모델링 (The Modeling of the Transistor Saturation Current of the BJT for Integrated Circuits Considering the Base)

  • 이은구;김태한;김철성
    • 대한전자공학회논문지SD
    • /
    • 제40권4호
    • /
    • pp.13-20
    • /
    • 2003
  • 반도체 소자이론에 근거한 집적회로용 BJT의 역포화 전류 모델을 제시한다. 공정 조건으로부터 베이스 영역의 불순물 분포를 구하는 방법과 원형 에미터 구조를 갖는 Lateral PNP BJT와 Vertical NPN BJT의 베이스 Gummel Number를 정교하게 계산하는 방법을 제시한다. 제안된 방법의 타당성을 검증하기 위해 20V와 30V 공정을 기반으로 제작한 NPN BJT와 PNP BJT의 역포화 전류를 실측치와 비교한 결과, NPN BJT는 6.7%의 평균상대오차를 보이고 있으며 PNP BJT는 6.0%의 평균 상태오차를 보인다.

3차원 정상상태의 드리프트-확산 방정식의 해석 프로그램 개발 (A development of the 3-dimensional stationary drift-diffusion equation solver)

  • 윤현민;김태한;김대영;김철성
    • 전자공학회논문지D
    • /
    • 제34D권8호
    • /
    • pp.41-51
    • /
    • 1997
  • The device simulator (BANDIS) which can analyze efficiently the electrical characteristics of the semiconductor devices under the three dimensional stationary conditions on the IBM PC was developed. Poisson, electon and hole continuity equations are discretized y te galerkin method using a tetrahedron as af finite element. The frontal solver which has exquisite data structures and advanced input/output functions is dused for the matrix solver which needs the highest cost in the three dimensional device simulation. The discretization method of the continuity equations used in BANDIS are compared with that of the scharfetter-gummel method used in the commercial three-dimensional device. To verify an accuracy and the efficiency of the discretization method, the simulation results of the PN junction diode and the BJT from BANDIS are compared with those of the commercial three-dimensiional device simulator such as DAVINCI. The maximum relative error within 2% and the average number of iterations needed for the convergence is decreased by more than 20%. The total simulation time of the BJT with 25542 nodes is decreased to about 60% compared with that of DAVINCI.

  • PDF

Development of an Improved Numerical Methodology for Design and Modification of Large Area Plasma Processing Chamber

  • 김호준;이승무;원제형
    • 한국진공학회:학술대회논문집
    • /
    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
    • /
    • pp.221-221
    • /
    • 2014
  • The present work proposes an improved numerical simulator for design and modification of large area capacitively coupled plasma (CCP) processing chamber. CCP, as notoriously well-known, demands the tremendously huge computational cost for carrying out transient analyses in realistic multi-dimensional models, because electron dissociations take place in a much smaller time scale (${\Delta}t{\approx}10-8{\sim}10-10$) than time scale of those happened between neutrals (${\Delta}t{\approx}10-1{\sim}10-3$), due to the rf drive frequencies of external electric field. And also, for spatial discretization of electron flux (Je), exponential scheme such as Scharfetter-Gummel method needs to be used in order to alleviate the numerical stiffness and resolve exponential change of spatial distribution of electron temperature (Te) and electron number density (Ne) in the vicinity of electrodes. Due to such computational intractability, it is prohibited to simulate CCP deposition in a three-dimension within acceptable calculation runtimes (<24 h). Under the situation where process conditions require thickness non-uniformity below 5%, however, detailed flow features of reactive gases induced from three-dimensional geometric effects such as gas distribution through the perforated plates (showerhead) should be considered. Without considering plasma chemistry, we therefore simulated flow, temperature and species fields in three-dimensional geometry first, and then, based on that data, boundary conditions of two-dimensional plasma discharge model are set. In the particular case of SiH4-NH3-N2-He CCP discharge to produce deposition of SiNxHy thin film, a cylindrical showerhead electrode reactor was studied by numerical modeling of mass, momentum and energy transports for charged particles in an axi-symmetric geometry. By solving transport equations of electron and radicals simultaneously, we observed that the way how source gases are consumed in the non-isothermal flow field and such consequences on active species production were outlined as playing the leading parts in the processes. As an example of application of the model for the prediction of the deposited thickness uniformity in a 300 mm wafer plasma processing chamber, the results were compared with the experimentally measured deposition profiles along the radius of the wafer varying inter-electrode gap. The simulation results were in good agreement with experimental data.

  • PDF