• Title/Summary/Keyword: Graph Theory

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A Study on the rapid calculating of reliability for Fault Tree (FT의 빠른 신뢰도계산을 위한 연구)

  • 이일재;이광원
    • Journal of the Korean Society of Safety
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    • v.12 no.4
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    • pp.180-190
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    • 1997
  • A new method in the fault tree analysis (FTA) for the reliability calculation is suggested. Two steps are necessary in traditional method in evaluation of the occurrence probability of top event in fault tree (FT). The first step is to find the minimal outsets, and the second one is to substitute the result into the poincare equation. In order to reduce the enormous computing time of this method, lots of rapid algorithms have been developed. Almost of all achievements were, however, based on the partial structural properties of FT. In this paper, the FT is transformed to a non-linear graph G which has the same minimal outsets of original n, and then the reliability is calculated using the domination theory. In this new method, the required number of equation terms are at most $2^n$ (n is node number of graph G), while $2^m$-1 (m is the number of minimal cutsets) calculation terms are required in the poincare equation in traditional method. Since m>>n in general. our new method reduces the calculation time significantly.

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The Fibonacci Edge Labelings on Fibonacci Trees (피보나치트리에서 피보나치 에지 번호매김방법)

  • Kim, Yong-Seok
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.6
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    • pp.437-450
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    • 2009
  • In this paper, we propose seven edge labeling methods. The methods produce three case of edge labels-sets of Fibonacci numbers {$F_k|k\;{\geq}\;2$}, {$F_{2k}|k\;{\geq}\;1$} and {$F_{3k+2}|k\;{\geq}\;0$}. When a sort of interconnection network, the circulant graph is designed, these edge labels are used for its jump sequence. As a result, the degree is due to the edge labels.

Petersen-Torus(PT) Network for Multicomputing System (멀티컴퓨팅 시스템을 위한 피터슨-토러스(PT) 네트워크)

  • Seo, Jung-Hyun;Lee, Hyeong-Ok;Jang, Moon-Suk
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.6
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    • pp.263-272
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    • 2008
  • We propose and analyze a new interconnection network, called petersen-torus(PT) network based on well-known petersen graph. PT network has a smaller diameter and a smaller network cost than honeycomb torus with same number of nodes. In this paper, we propose optimal routing algorithm and hamiltonian cycle algorithm. We derive diameter, network cost and bisection width.

A Combinational Method to Determining Identical Entities from Heterogeneous Knowledge Graphs

  • Kim, Haklae
    • Journal of Information Science Theory and Practice
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    • v.6 no.3
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    • pp.6-15
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    • 2018
  • With the increasing demand for intelligent services, knowledge graph technologies have attracted much attention. Various application-specific knowledge bases have been developed in industry and academia. In particular, open knowledge bases play an important role for constructing a new knowledge base by serving as a reference data source. However, identifying the same entities among heterogeneous knowledge sources is not trivial. This study focuses on extracting and determining exact and precise entities, which is essential for merging and fusing various knowledge sources. To achieve this, several algorithms for extracting the same entities are proposed and then their performance is evaluated using real-world knowledge sources.

A Computer Aided Automatic Verification System for Mechanical Drawings Drawn with CAD System (CAD 시스템에 의하여 작성된 기계도면의 자동검증시스템에 관한 연구)

  • Lee, S.S.
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.8
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    • pp.60-71
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    • 1996
  • Mostof existing CAD systems do not provide the advanced function for systematic checking of design and drafting errors in mechanical drawings. We have reported a computer aided drawing check system to single plane projection drawings made by a CAD system. This paper describes a checking method of dimensioning errors in mechanical drawings. The checking items are deficiency and redundancy of dimensions, input-errors in dimension figures and symbols, etc. Checking for deficiency and redundancy of global dimensions has been performed applying Graph Theory. This system has been applied to several examples and we have confirmed the feasibility of this checking method.

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Reconfiguration method for Supervisor Control in Deadlock status Using FSSTP(Forbidden Sequence of State Transition Problem) (순차상태전이금지(FSSTP)를 이용한 교착상태 관리제어를 위한 재구성 방법)

  • Song, Yu-Jin;Lee, Eun-Joo;Lee, Jong-Kun
    • Journal of Institute of Control, Robotics and Systems
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    • v.14 no.3
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    • pp.213-220
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    • 2008
  • The object of this paper is to propose a method to deal with the problem of modeling user specifications in approaches based on supervisory control and Petri nets. However, most of Petri Net approaches are based on forbidden states specifications, and these specifications are suitable the use of tool such as the reachability graph. But these methods were not able to show the user specification easily and these formalisms are generally limited by the combinatorial explosion that occurs when attempting to model complex systems. Herein, we propose a new efficient method using FSSTP (Forbidden Sequences of State-Transitions Problem) and theory of region. Also, to detect and avoid the deadlock problem in control process, we use DAPN method (Deadlock Avoidance Petri nets) for solving this problem in control model.

A Study on the Optimal Facility Layout Design Using an Improved Genetic Algorithm (개선된 유전자 알고리즘을 이용한 최적 공간 배치 설계에 관한 연구)

  • 한성남;이규열;노명일
    • Korean Journal of Computational Design and Engineering
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    • v.6 no.3
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    • pp.174-183
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    • 2001
  • This study proposes an improved genetic algorithm (GA) to derive solutions for facility layout problems having inner walls and passages. The proposed algorithm models the layout of facilities on a flour-segmented chromosome. Improved solutions are produced by employing genetic operations known as selection, crossover, inversion, mutation, and refinement of these genes for successive generations. All relationships between the facilities and passages are represented as an adjacency graph. The shortest path and distance between two facilities are calculated using Dijkstra's algorithm of graph theory. Comparative testing shows that the proposed algorithm performs better than other existing algorithm for the optimal facility layout design. Finally, the proposed algorithm is applied to ship compartment layout problems with the computational results compared to an actual ship compartment layout.

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A Linear Clustering Method for the Scheduling of the Directed Acyclic Graph Model with Multiprocessors Using Genetic Algorithm (다중프로세서를 갖는 유방향무환그래프 모델의 스케쥴링을 위한 유전알고리즘을 이용한 선형 클러스터링 해법)

  • Sung, Ki-Seok;Park, Jee-Hyuk
    • Journal of Korean Institute of Industrial Engineers
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    • v.24 no.4
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    • pp.591-600
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    • 1998
  • The scheduling of parallel computing systems consists of two procedures, the assignment of tasks to each available processor and the ordering of tasks in each processor. The assignment procedure is same with a clustering. The clustering is classified into linear or nonlinear according to the precedence relationship of the tasks in each cluster. The parallel computing system can be modeled with a Directed Acyclic Graph(DAG). By the granularity theory, DAG is categorized into Coarse Grain Type(CDAG) and Fine Grain Type(FDAG). We suggest the linear clustering method for the scheduling of CDAG using the genetic algorithm. The method utilizes a properly that the optimal schedule of a CDAG is one of linear clustering. We present the computational comparisons between the suggested method for CDAG and an existing method for the general DAG including CDAG and FDAG.

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Node-reduction Model of Large-scale Network Grape (대형 회로망 그래프 마디축소 모델)

  • Hwang, Jae-Ho
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.50 no.2
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    • pp.93-99
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    • 2001
  • A new type geometric and mathematical network reduction model is introduced. Large-scale network is analyzed with analytic approach. The graph has many nodes, branches and loops. Circuit equation are obtained from these elements and connection rule. In this paper, the analytic relation between voltage source has a mutual different graphic property. Node-reduction procedure is achieved with this circuit property. Consequently voltage source value is included into the adjacent node-analyzing equation. A resultant model equations are reduced as much as voltage source number. Matrix rank is (n-1-k), where n, k is node and voltage source number. The reduction procedure is described and verified with geometric principle and circuit theory. Matrix type circuit equation can be composed with this technique. The last results shall be calculated by using computer.

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AGV Deadlock Avoidance Under Zone Control (존 조정하에서의 AGV 고착 방지)

  • Yim, Dong-Soon
    • Journal of Korean Institute of Industrial Engineers
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    • v.26 no.4
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    • pp.392-401
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    • 2000
  • In this work, a deadlock avoidance strategy is proposed in order to effectively handle conflicts and deadlocks occurring in zone-control AGV (Automated Guided Vehicle) systems. The basic idea is based on Capacity-designated Directed Graph (CDG) theory that was developed to avoid from deadlocks in manufacturing systems. However, to enforce the effectiveness of detecting impending and restricted deadlocks, AGV routings are explicitly described in Extended Directed Graph (EDG). From EDG, a non-conservative deadlock-avoidance strategy is derived. The superiority of the proposed strategy lies on the applicability to diverse AGV path configurations using zone control. Also, because of its insensibility and robustness, it can be effectively used when the system has randomness and stochastic nature.

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