• ETRI Journal
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• 제21권3호
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• pp.16-21
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• 1999

After etching Al-Cu alloy films using SiCl4/Cl_2/He/CHF3 mixed gas plasma, the corrosion phenomenon at the grain boundary of the etched surface and a passivation layer on the etched surface with an SF6 plasma treatment subsequent to the etching were studied. In Al-Cu alloy system, corrosion occurs rapidly on the etched surface by residual chlorine atoms, and it occurs dominantly at the grain boundaries rather than the crystalline surfaces. To prevent corrosion, the SF6 gas plasma treatment subsequent to etching was carried out. The passivation layer is composed of fluorine-related compounds on the etched Al-Cu surface after the SF6 treatment, and it suppresses effectively corrosion on the surface as the SF6 treatment pressure increases. Corrosion could be suppressed successfully with the SF6 treatment at a total pressure of 300 mTorr. To investigate the reason why corrosion could be suppressed with the SF6 treatment, behaviors of chlorine and fluorine were studied by various analysis techniques. It was also found that the residual chlorine incorporated at the grain boundary of the etched surface accelerated corrosion and could not be removed after the SF6 plasma treatment.

• 한국전기전자재료학회논문지
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• 제12권1호
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• pp.35-43
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• 1999

Microstructures and dielectric properties of (Sr$\_$1-x/Ca$\_$x/) TiO$_3$-0.006Nb$_2$O$\_$5/ (0.05$\leq$x$\leq$0.2) boundary layer ceramics were investigated. The samples fired in a reducing atmosphere(N$_2$) were painted on the surface with CuO paste for the subsequent grain boundary diffusion, and then annealed at 1100$^{\circ}C$ for 2 hrs. The metal oxide of CuO infiltrated by thermal diffusion from surface of sample presents continuously in not grain but only grain boundary, and makes up thin boundary phase. The SEM photo, and EDAX revealed that CuO was penetrated rapidly into the bulk along the grain boundaries during the annealing. The average grain sizes is continuously increased as the content of substitutional Ca is increased from 5[mol%] to 15[mol%], but the average grain size of the sample with content of 20[mol%] Ca is slightly decreased. In the samples with content of 10∼15[mol%] Ca, excellent dielectric properties were obtained as follows; dielectric constant <25000, dielectric loss <0.3[%], and capacitance change rate as a function of temperature <${\pm}$10[%], respectively. All samples in this study exhibited dielectric relaxation with frequency as a functior of the temperature.

• 한국전기전자재료학회논문지
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• 제15권4호
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• pp.332-337
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• 2002

The applicability of models based on fractal geometry to characterize the surface of the EL devices was investigated. Insulating layer and phosphor layer of EL devices were deposited on ITO glass using e-beam method. The images of phosphor layer by scanning electron microscope(SEM) were transformed to binary coded data. The relations between fractal geometry and electrical characteristics of EL devices were investigated. When the fractal dimension of $Cas:EuF_3$ EL device was 1.82 and its grain boundary area was 19%, the brightness of $Cas:EuF_3$ EL device was 261 cd/$\textrm{m}^2$.

• Journal of Advanced Marine Engineering and Technology
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• 제30권8호
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• pp.907-918
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• 2006

In this study capacitance and dielectric loss factor were measured with low-voltage signal and the simulation of equivalent circuits for the data was conducted. As the result it was shown that the equivalent circuit model considered the grain-boundary structure with semiconducting layer, dielectric layer and depletion layer was well approximated with the observed data. Various parameters were determined by a optimum curve-fitting method and could be used to analyze the characteristics of varistor. It also seems that the proposed equivalent circuit model will be adopted for other BL type varistors.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.185-188
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• 1999

Biepitaxial Y$_1Ba_2Cu_3O_{7-x}$ (YBCO) and La$_{0.2}Sr_{0.8}MnO_3$ (LSMO) thin films have been prepared on SrTiO$_3$ buffer layer and MgO seed layer grown on Al$_2O_3$(11${\bar{2}}$0)substrates by dc-sputtering with hollow cylindrical targets, respectively. We charaterized Josephson properties and significantly large magnetoresistance in YBCO and LSMO films with 45$^{\circ}$ grain boundary junction, respectively. The observed working voltage (I$_cR_n$) at 77 K in grain boundary junction was below 10${\mu}$V, which is typical I$_cR_n$ value of single biepitaxial Josephson junction. The field magnetoresistance ratio (MR) of LSMO grain boundary juncoon at 77K was enhanced to 13%, which it was significant MR value with high magnetic field sensitivity at a low field of 250 Oe. These results indicate that inserting the insulating layer instead of the grain boundary layer with metallic phase can be possible to apply a new SIS Josephson junction and a novel magnetic device using spin-polarized tunneling junction.

• E2M - 전기 전자와 첨단 소재
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• 제9권4호
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• pp.396-403
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• 1996

In this paper, the (S $r_{0.85}$.C $a_{0.15}$)Ti $O_{3}$ of paraelectric grain boundary layer (GBL) ceramics were fabricated, and the analysis of microstructuye and the thermally stimulated current(TSC) were investigated for understanding effects of GBL's interfacial phenomenon on variations of electrical properties. As a result, the three peaks of .alpha., .alpha. and .betha. were obtained at the temperature of -20 [.deg. C], 20[.deg. C] and 80[.deg. C], respectively. The origins of these peaks are that the .alpha. peak observed at -20[.deg. C] looks like to be ascribed to the ionization excitation from donor level in the grain, and the .alpha.' peak observed at 20[.deg. C] appears to show up by detrap of the trapped carrier of border between the oxidation layer and the grain, and the .betha. peak observed at 80[.deg. C] seems to be resulted from hopping conduction of existing carrier in the trap site of the border between the oxidation and second phase. and second phase.

• 한국전기전자재료학회논문지
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• 제25권2호
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• pp.85-90
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• 2012

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.34-37
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• 2001

In this study, the capacitance-voltage properties of $(Sr_{1-x}\cdot Ca_x)TiO_3(0.05{\leq}x{\leq}0.20)$-based grain boundary layer ceramics were investigated. The ceramics were fabricated by the conventional mixed oxide method. The sintering temperature and time were $1480\sim1500^{\circ}C$ and 4 hours. respectively. The 2nd phase formed by the thermal diffusion of CuO from the surface leads to very excellent dielectric properties, that is, ${\varepsilon}_r$ >50000, tan$\delta$ <0.05, ${\Delta}C$ < ${\pm}10%.$ The capacitance is almost unchanged below about 20[V] but it decreases slowly about 20[V]. The results of the capacitance-voltage properties indicated that the grain boundary was composed of the continuous insulating layers.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.209-212
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• 1995

In this paper, the $(Sr_{0.85}{\cdot}Ca_{0.15})TiO_3$ of paraelectric grain boundary layer (GBL) ceramics were fabricated. The characteristics of electrical conduction and the thermally stimulated current(TSC) were measured respectively. The region I below 200[V/cm] shows the ohmic conduction, the region II between 200[V/cm] and 1000[V/cm] can be explained by the Pool-Frenkel emission theory, and the region III above 2000[V/cm] is dominated by the tunneling effect. As a result, The origins of these peaks are that the ${\alpha}$ peak observed at $-20[^{\circ}C]$ looks like to be ascribed to the ionization excitation from donor level in the grain, and the ${\alpha}^{\prime}$ peak observed at $-20[^{\circ}C]$ appears to show up by detrap of the trapped carrier of border between the oxidation layer and the grain, and the ${\beta}$ peak observed at $80[^{\circ}C]$ seems to be resulted from hopping conduction of existing carrier in the trap site of the border between the oxidation and second phase.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.430-430
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• 2010

MICC 방법으로 제작된 TFT는 large grain과 그에 따른 grain boundary의 감소로 인하여여, 소자의 전기적 특성을 좋게 할 수 있다. 본 연구에서는 bi-layer channel의 large grain size TFT를 제작하여 소자의 전기적 특성을 비교하였다. Channel의 width / length의 크기는 각 각의 경우 $7/5{\times}2$, $10/5{\times}2$, $15/5{\times}2$ (${\mu}m$)로 하였다. 소자의 성능 측정 결과 Field-effect mobility의 경우에는 channel width가 증가할 수록 감소하는 경향성을 나타내었으며, Threshold voltage의 경우에는 조금 감소하는 경향성은 있었으나 변화의 폭이 매우 작았다. Output characteristics 의 경우에는 모든 set에서 좋은 saturation 특성을 보였다. 이것은 current croding이 없었다는 것을 의미하는데, 큰 grain size로 인한 효과로 해석 할 수 있다. 본 연구에서는 bi-layer channel에서 corner effect에 중점을 두어 소자의 전기적 특성 변화에 대하여 논하였다.