• Title/Summary/Keyword: Graded layer

검색결과 242건 처리시간 0.027초

Computer-simulation with Different Types of Bandgap Profiling for Amorphous Silicon Germanium Thin Films Solar Cells

  • 조재현;이준신
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.320-320
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    • 2014
  • Amorphous silicon alloy (a-Si) solar cells and modules have been receiving a great deal of attention as a low-cost alternate energy source for large-scale terrestrial applications. Key to the achievement of high-efficiency solar cells using the multi-junction approach is the development of high quality, low band-gap materials which can capture the low-energy photons of the solar spectrum. Several cell designs have been reported in the past where grading or buffer layers have been incorporated at the junction interface to reduce carrier recombination near the junction. We have investigated profiling the composition of the a-SiGe alloy throughout the bulk of the intrinsic material so as to have a built-in electrical field in a substantial portion of the intrinsic material. As a result, the band gap mismatch between a-Si:H and $a-Si_{1-x}Ge_x:H$ creates a barrier for carrier transport. Previous reports have proposed a graded band gap structure in the absorber layer not only effectively increases the short wavelength absorption near the p/i interface, but also enhances the hole transport near the i-n interface. Here, we modulated the GeH4 flow rate to control the band gap to be graded from 1.75 eV (a-Si:H) to 1.55 eV ($a-Si_{1-x}Ge_x:H$). The band structure in the absorber layer thus became like a U-shape in which the lowest band gap was located in the middle of the i-layer. Incorporation of this structure in the middle and top cell of the triple-cell configuration is expected to increase the conversion efficiency further.

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Dynamic analysis of laminated nanocomposite pipes under the effect of turbulent in viscoelastic medium

  • Ghaitani, M.M.;Majidian, A.;Shokri, V.
    • Wind and Structures
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    • 제30권2호
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    • pp.133-140
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    • 2020
  • In this paper, critical fluid velocity and frequency of laminated pipe conveying fluid are presented. Each layer of the pipe is reinforced by functionally graded carbon nanotubes (FG-CNTs). The internal fluid is assumed turbulent and the induced forces are calculated by momentum equations. The pipe is resting on viscoelastic foundation with spring, shear and damping constants. The motion equations are derived based on classical shell theory and energy method. Differential quadrature method (DQM) is used for solution and obtaining the critical fluid velocity. The effects of volume percent and distribution of CNT, boundary condition, lamina layer number, length to radius ration of pipe, viscoelastic medium and fluid velocity are shown on the critical fluid velocity. Results show that with increasing the lamina layer number, the critical fluid velocity increases.

Reduction of Contact Resistance Between Ni-InGaAs Alloy and In0.53Ga0.47As Using Te Interlayer

  • Li, Meng;Shin, Geon-Ho;Lee, Hi-Deok;Jun, Dong-Hwan;Oh, Jungwoo
    • Transactions on Electrical and Electronic Materials
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    • 제18권5호
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    • pp.253-256
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    • 2017
  • A thin Te interlayer was applied to a Ni/n-InGaAs contact to reduce the contact resistance between Ni-InGaAs and n-InGaAs. A 5-nm-thick Te layer was first deposited on a Si-doped n-type $In_{0.53}Ga_{0.47}As$ layer, followed by in situ deposition of a 30-nm-thick Ni film. After the formation of the Ni-InGaAs alloy by rapid thermal annealing at $300^{\circ}C$ for 30 s, the extracted specific contact resistivity (${\rho}_c$) reduced by more than one order of magnitude from $2.86{\times}10^{-4}{\Omega}{\cdot}cm^2$ to $8.98{\times}10^{-6}{\Omega}{\cdot}cm^2$ than that of the reference sample. A thinner Ni-InGaAs alloy layer with a better morphology was obtained by the introduction of the Te layer. The improved interface morphology and the graded Ni-InGaAs layer formed at the interface were believed to be responsible for ${\rho}_c$ reduction.

Vibration response of FG-CNT-reinforced plates covered by magnetic layer utilizing numerical solution

  • Cao, Yan;Musharavati, Farayi;Baharom, Shahrizan;Talebizadehsardari, Pouyan;Sebaey, Tamer A.;Eyvazian, Arameh;Zain, Azlan Mohd
    • Steel and Composite Structures
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    • 제37권2호
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    • pp.253-258
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    • 2020
  • Vibration response in a sandwich plate with a nanocompiste core covered by magnetic layer is presented. The core is armed by functionalyy graded-carbon nanotubes (FG-CNTs) where the Mori-Tanaka law is utilized assuming agglomeration effects. The structure plate is located on elastic medium simulated by Pasternak model. The governing equations are derived based on Mindlin theory and Hamilton's principle. Utilizing diffrential quadrature method (DQM), the frequency of the structure is calculated and the effects of magnetic layer, volume percent and agglomeration of CNTs, elastic medium and geometrical parameters of structure are shown on the frequency of system. Results indicate that with considering magnetic layer, the frequency of structure is increased.

Assessment Corrosion and Bioactive Behavior of Bioglass Coating on Co-Cr-Mo Alloy By Electrophoretic Deposition For Biomedical Applications

  • Areege K. Abed;Ali. M. Mustafa;Ali M. Resen
    • Corrosion Science and Technology
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    • 제23권3호
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    • pp.179-194
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    • 2024
  • A layer-by-layer coating was produced using electrophoretic deposition for a HA/Al2O3 coating layer and a bioglass coating layer on Co-Cr-Mo alloy with a roughness of 0.5 ㎛ (400 emery paper SiC). The corrosion behaviour was analyzed by assessing the coating layers' exceptional corrosion resistance, which outperformed the substrate. Cr ion release test using AAS was carried out, indicating that factional graded coating inhibited ion release from the uncoated substrate to coated sample. The porosity was expressed as a percentage, representing the extent of imperfections on the surface of all coatings. These imperfections fell within an acceptable range of 1% to 3%. The roughness of the coated surface was measured using atomic force microscopy, which revealed an excellent roughness value of 3.32 nm. Tape test technique for adhesion revealed that the removal area of the substrate coating layer varied by 11.92%. X-ray diffraction analysis confirmed the presence of all coating material peaks and verified phases of the deposited coating layers. These findings provided evidence that the coating composition remains unaffected by the electrophoretic deposition process. The bioactivity was assessed by immersion in a simulated bodily fluid, which revealed the formation of HCA during a period of 5 days.

NH$_3$-pplasma Treatment of GaAs Surface at High Tempperature in RF pparallel pplate pplasma Reactor

  • ppark, Kyoung-Wan;Lee, Seong-Jae-;Kim, Gyungock-;Lee, El-Hang-
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 1993년도 제4회 학술발표회 논문개요집
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    • pp.29-31
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    • 1993
  • NH3-pplasma treatment has been used for ppassivation of native-oxide-contaminated GaAs surface. Ex-situ band-gapp pphotoluminescence(ppL) measurement shows enhanced intensity for the treated surfaces. Auger electron sppectroscoppy(AES) shows that the treated surface contains nitrogen atoms but no arsenic atoms, which leads us to sppeculate that the graded GaN thin layer was formed on the surface. Based on these results, new metal-insulator-GaAs structure is ppropposed.

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Bottom 컬렉터와 단일 금속층 구조로 설계된 SiGe HBT의 전기적 특성 (Electrical Properties of SiGe HBTs designed with Bottom Collector and Single Metal Layer Structures)

  • 최아람;최상식;김준식;윤석남;김상훈;심규환
    • 한국전기전자재료학회논문지
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    • 제20권8호
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    • pp.661-665
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    • 2007
  • This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence $(<200^{\circ}C)$ on electrical properties. The feasible application in $1{\sim}2GHz$ frequency from measured data $BV_{CEO}{\sim}10V,\;f_T{\sim}14GHz,\;{\beta}{\simeq}110,\;NF{\sim}1dB$ using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

InAlGaAs/InGaAs HBT의 Monte carlo 해석 (Monte carlo analysis of InAlGaAs/InGaAs HBT)

  • 황성범;김용규;송정근
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 하계종합학술대회논문집
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    • pp.405-408
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    • 1998
  • Due to the large conduction band discontinuity between emitter base, OmGaAs HBT has an advantge to enable the hot electrons to inject into the base. In this paper, InAlGaAs/InGaAs HBT with the various emitter junction gradings and the modified collectors are simulated and analyzed by HMC(hybrid monte carlo) simulator in order to find a optimal structure for the shortest transit time. A minium base transit time (.tau.$_{b}$ ) of 0.21 ps was obtained for HBT with the grading layer, which is parabolically graded from x=1.0 to x=0.5. The minimum collector transit time (.tau.$_{c}$ ) of 0.31ps was found when the collector was modified by inserting p$^{[-10]}$ and p$^{+}$ layers. Thus HBT in combination with the emitter grading and the modified collector layer showed the cut-off frequency (f$_{T}$) of 183GHz.z.z.

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다양한 기울기를 갖는 TEOS 필드 산화막의 경사식각 (Tapered Etching of Field Oxide with Various Angle using TEOS)

  • 김상기;박일용;구진근;김종대
    • 한국전기전자재료학회논문지
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    • 제15권10호
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    • pp.844-850
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    • 2002
  • Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.