• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.27-36
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• 2004

In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.648-654
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• 2002

The Virtual Interface Architecture(VIA) is an industry standard for communication over system area networks(SANs). M-VIA is a software implementation of VIA technology on Linux. In this paper, we implemented the M-VIA on an AceNIC Gigabit Ethernet by developing a new AceNIC driver for the M-VIA. We analyzed the M-VIA data segmentation processes. When a Gigabit Ethernet MTU is larger than 1514 bytes, M-VIA data segmentation size leaves much room for improvement. So we experimented with various MTU and M-VIA data segmentation size and compared the performances.

• Journal of Internet Computing and Services
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• v.22 no.5
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• pp.17-26
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• 2021

This paper is about a physical layer frame security technique using OFB-style encryption/decryption with AES algorithms on Gigabit Ethernet network. We propose a data security technique at the physical layer that performs OFB-style encryption/decryption with AES algorithm with strong security strength when sending and receiving data over Gigabit Ethernet network. Generally, when operating Gigabit Ethernet network, there is no security features, but data security is required, additional devices that apply this technique can be installed to perform security functions. In the case of data transmission over Gigabit Ethernet network, the Ethernet frames conform to IEEE 802.3 specification, which includes several fields to ensure proper reception of data at the receiving node in addition to the data field. When encrypting, only the data field should be encrypted and transmitted in real time. In this paper, we show that only the data field of the IEEE802.3 frame is encrypted and transmitted on the sending node, and only the data field is decrypted to show the plain text on the receiving node, which shows that the encryption/decryption is carried out correctly. Therefore, additional installation of devices that apply this technique can increase the reliability of the system when security for data is required in Ethernet network operating without security features.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.371-378
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• 2004

This paper presents the implementation and performance of the HVIA-GE card, which is a hardware implementation of the Virtual Interface Architecture (VIA) based on Gigabit Ethernet. The HVIA-GE card is a 32-bit/33MHz PCI adapter containing an FPGA for the VIA protocol engine and a Gigabit Ethernet chip set to construct a high performance physical network. HVIA-GE performs virtual-to-physical address translation, Doorbell, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the HVIA-GE card, and the VIA protocol engine efficiently controls the address translation process by directly accessing the ATT. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show the maximum bandwidth of 93.7MB/s and the minimum latency of 11.9${\mu}\textrm{s}$. In terms of minimum latency HVIA-GE performs 4.8 times and 9.9 times faster than M-VIA and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of HVIA-GE is 50.4% and 65% higher than M-VIA and TCP/IP respectively.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.378-381
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• 2003

This paper presents a design and implementation of 10gigabit ethernet frame multiplexer/demultiplexer. In this paper, we discuss gigabit and 10 gigabit ethernet standard interfaces(GMII/XGMII) and we propose multiple gigabit ethernet frame multiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then 10gigabit ethernet frame MUX/DMUX is designed, verified and implemented using FPGA.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.359-362
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• 2002

In this paper, we propose a structure of 800bps high speed router and a gigabit Ethernet line interface board. Having Programmability, network processor is applied to gjgabit Ethernet line interface board. Also, we propose a new method to upgrade image files that consist of operating system and drivers. It is possible to upgrade image files for several boards at once and to reduce the elapsed time for image upgrade using tile proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1470-1474
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• 2001

8B/10B 선로부호를 채택한 기가비트 이더넷 PCS 수신측에서는 동기부의 바이트 동기획득과 수신부의 디코딩을 위해 Running Disparity(RD) 에러인 데이터열을 검출해야 한다. 기존의 RD 에러 검출 방법은 직렬 입력 비트에서 RD 에러를 검출하였으나 제안하는 RD 에러 검출 방법은 125MHz 속도의 10비트 데이터열을 받아 4비트열과 6비트열로 나누어 바이트 클럭에 따라 RD를 계산하고 계산된 이전의 RD값과 현재의 RD값을 비교하며 RD 위반 에러 데이터를 검출한다. 이는 기존의 RD 에러 검출 방법이 비트 클럭과 니블 클럭에 따라 RD 에러를 검출하기 때문에 야기되는 초고속 처리에 대한 한계를 해결한 것이며 기가비트 이더넷에 적합한 새로운 RD 에러 검출 방법이다.

• The Journal of the Korea Contents Association
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• v.2 no.3
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• pp.96-104
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• 2002

This paper has done a network performance test as well as result analysis of the test in a real campus gigabit network The inner network backbone consists of gigabit ethernet . The mean ratio of network use is below 1% age, and the maximum one comes to 10%. The floating capacity is still good enough to meet network flowing because the mean ratio of inner campus network as outer ones is 30.4% and the maximum one is merely 38.3%. But there appears a security problem. We must make a device blocking illegal approach to the client form outer network It is important that we can a away to manage the campus gigabit network efficiently on the basis of the given data from this performance test.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.5
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• pp.37-43
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• 2003

Parallel computing method is widely used in the computational fluid dynamics for efficient numerical analysis. Nowadays, low cost Linux cluster computers substitute for traditional supercomputers with parallel computing shcemes. The performance of nemerical solvers on an Linux cluster computer is highly dependent not on the performance of processors but on the performance of network devices in the cluster system. In this paper, we investigated the effects of the network devices such as Myrinet2000, gigabit ethernet, and fast ethernet on the performance of the cluster system by using some benchmark programs such as Netpipe, LINPACK, NAS NPB, and MPINS2D Navier-Stokes solvers. Finally, upon this investigation, we will suggest the method for building high performance low cost Linux cluster system in the computational fluid dynamics analysis.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.799-802
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• 1998

As we know, gigabit ethernet is a new technology to be substituted for current fast ethernet used widely in local area network. The switch used in gigabit ethernet should deal with frames in giga-bps. To do such a fast switching, we need that serveral processes meet the budgets, such as MAC address table lookup, several giga speed path setup, fast scheduling, and etc. Especially MAC address table lookup has to be processed in the same speed with speed of incoming packets, thus the bottleneck in the process can cause packet loss by the overflow in the input buffer. We devise new practical hardware hashing method to perform fast table lookup by minimizing the number of external memory access and accelerating with hardware.