• Title/Summary/Keyword: Gettering

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A Study on Secondary Defects in Silicon after 2-step Annealing of the High Energy $^{75}AS^+$ Ion Implanted Silicon (고에너지비소 이온 주입후 2단계 열처리시 2차결함에 대한 연구)

  • 윤상현;곽계달
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.10
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    • pp.796-803
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    • 1998
  • Intrinsic and proximity gettering are popular processes to get higher cumulative production yield and usually adopt multi-step annealing and high energy ion implantation, respectively. In order to test the combined processed of these, high energy \ulcornerAs\ulcorner ion implantation and 2-step annealing process were adopted. After the ion implantation followed by 2-step annealing, the wafers were cleaved and etched with Wright etchant. The morphology of cross section on samples was inspected by FESEM. The concentration profile of As was measured by SRP. The location and type of secondary defects inspected by HRTEM were dependent on the 1st annealing temperatures. That is, a line of dislocation located at $1.5mutextrm{m}$ apart from the surface at $600^{\circ}C$ lst annealing was changed to some dislocation lines or loops nearby the surface at 100$0^{\circ}C$. The density of dislocation line was reduced but the size of the defects was enlarged as the temperature increased.

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A Study on High Energy Ion Implantation for Retrograde Well Formation (Retrograde Well 형성을 위한 고에너지 이온주입에 대한 연구)

  • 윤상현;곽계달
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.5
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    • pp.358-364
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    • 1998
  • Retrograde well is a new process for ULSI fabrication. High energy ion implantation has been used for retrograde well formation. In this paper the forming condition for retrograde well using high energy ion implantation is compared with that for conventional well. TW signals for retrograde p-,n-well($900^{\circ}C$),after annealing are similar trends to those of conventional ones($1150^{\circ}C$), however the signals for RTA have the highest value because of small thermal budget. Junction depths of retrograde well are varied from about 1.2 to $3.0\{mu}m$ as for conventional well. The peak concentrations of retrograde well, however, are about 10 times higher in values than those of conventional ones so that they can be used as any types of potential barriers or gettering sites. The critical dose for phosphorus implantation in our experiments is between $3\times10^{13} and 1\times10^{14}/cm^2$. Under the above critical dose, there are many secondary defects near projected range such as dislocation lines and dislocation loops.

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Fabrication and Characteristics of $P^+N$ and $P^+NN^+$ Junction Silicon Solar Cell ($P^+N, P^+NN^+$ 접합형 실리콘 태양전지의 제작 및 특성)

  • Lee, Dae-U;Lee, Jong-Deok;Kim, Gi-Won
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.20 no.1
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    • pp.22-26
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    • 1983
  • P+N and P+NN+ solar cells with the area of 3.36 $\textrm{cm}^2$ were fabricated by thermal diffusion. Under the light intensity of 100 mW/$\textrm{cm}^2$, total area(active area) conversion efficiency was 13.4%(14.7%) for P+N cell fabricated by 15 min boron predeposition at 94$0^{\circ}C$ and 20 min annealing at 80$0^{\circ}C$, and 14.3%(15.6%) for P+NN+ cell processed by 15 min boron predeposition at 94$0^{\circ}C$ and 50 min annealing at 80$0^{\circ}C$ after 20 min back phosphorus diffusion at 1,05$0^{\circ}C$. The minority carrier lifetime in bulk of P+NN+ cells was increased about 2~3 times comparing with P+N cells because of guttering and BSF effect due to back phosphorus doping. The methods used for efficiency improvement were AR coating, Ag electroplating, back doping and fine grid pattern as well as the control of front doping profile.

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Moisture Gettering by Porous Alumina Films on Textured Silicon Wafer (실리콘 표면에 증착된 다공성 알루미나의 수분 흡착 거동)

  • Lim, Hyo Ryoung;Eom, Nu Si A;Cho, Jeong-Ho;Choa, Yong-Ho
    • Korean Chemical Engineering Research
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    • v.53 no.3
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    • pp.401-406
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    • 2015
  • Getter is a class of materials used in absorbing gases such as hydrogen and moisture in microelectronics or semiconductor devices to operate properly. In this study, we developed a new device structure consisting of porous anodized alumina films on textured silicon wafer, which have cost efficiency in materials and processing aspects. Anodic aluminum oxide (AAO) with controlled pore sizes can be applied to a high-efficiency moisture absorber due to the high surface area and OH- saturated surface property. The moisture sorption capacity was 2.02% (RH=35%), obtained by analyzing isothermal adsorption/desorption curve.

Defect Formatìon and Annealìng Behavìor in MeV Si Self-Implanted Silicon (MeV Si 자기 이온주입된 단결정 Silicon내의 결함 거동)

  • Cho, Nam-Hoon;Jang, Ki-Wan;Suh, Kyung-Soo;Lee, Jeoung-Yong;Ro, Jae-Sang
    • Korean Journal of Materials Research
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    • v.6 no.7
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    • pp.733-741
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    • 1996
  • In this study MeV Si self ion implantations were done to reveal the intrinsic behavior of defect formation by excluding the possibility of chemical interactions between substrate atoms and dopant ones. Self implantations were conducted using Tandem Accelerator with energy ranges from 1 to 3 MeV. Defect formation by high energy ion implantation has a significant characteristics in that the lattice damage is concentrated near Rp and isolated from the surface. In order to investigate the energy dependence on defect formation, implantation energies were varied from 1 to 3 MeV under a constant dose of $1{\times}10^{15}/cm^2$. RBS channe!ed spectra showed that the depth at which as-implanted damaged layer formed increases as energy increases and that near surface region maintains better crystallinity as energy increases. Cross sectional TEM results agree well with RBS ones. In a TEM image as-implanted damaged layer appears as a dark band, where secondary defects are formed upon annealing. In the case of 2 MeV $Si^+$ self implantation a critical dose for the secondary defect formation was found to be between $3{\times}10^{14}/cm^24$ and $5{\times}10^{14}/cm^2$. Upon annealing the upper layer of the dark band was removed while the bottom part of the dark band did not move. The observed defect behavior by TEM was interpreted by Monte Carlo computer simulations using TRIM-code. SIMS analyses indicated that the secondary defect formed after annealing gettered oxygen impurities existed in silicon.

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Characteristics of Silicon Rich Oxide by PECVD (PECVD에 의한 Sirich 산화막의 특성)

  • Gang, Seon-Hwa;Lee, Sang-Gyu;Park, Hong-Rak;Go, Cheol-Gi;Choe, Su-Han
    • Korean Journal of Materials Research
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    • v.3 no.5
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    • pp.459-465
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    • 1993
  • By making the inter-metal PECVD $SiO_2$ as a Si rich oxide under the SOG, the hydrogen and water related diffusants could be captured a t SI dangling bonds. This gettering process was known to prevent the device characteristics degradations related to the H, $H_20$. The basic characteristics of Si rich oxide have been studied according to changing high/low frequency power and $SiH_4/N_2O$ gas flow ratio in PECVD. As increase in low frequency power, deposition rate decreased but K.I. and compressive stress increased. Decrease of the water peaks of FTIR spectra at the wave number range of 3300~3800$\textrm{cm}^{-1}$' also indicated that intensty the films were densified. As increase in SiH, gas flow rate, deposition rate, R.I. and etch rate increased while compressive stress decreased. F'TIK spectra showed that peak intensity corresponding to Si-0-Si stretching vibration decreased and shifted to the lower wave numbers. But AES showed that Si dangl~ng bonds were increased as a result of lower Si:O(l: 1.23) ratlo inthe Si rich oxide as compared to Si : O(1 : 1.98) ratio of usual oxide.

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The Fabrication of Poly-Si Solar Cells for Low Cost Power Utillity (저가 지상전력을 위한 다결정 실리콘 태양전지 제작)

  • Kim, S.S.;Lim, D.G.;Shim, K.S.;Lee, J.H.;Kim, H.W.;Yi, J.
    • Solar Energy
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    • v.17 no.4
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    • pp.3-11
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    • 1997
  • Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.

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