• Title/Summary/Keyword: Gating System Design

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Die Design of Semi-Solid Forging by Computer Simulation and their Experimental Investigation (Computer Simulation에 의한 Semi-Solid 단조금형의 설계 및 실험적 검정)

  • Seo P. K.;Lee D. H.;Kang C. G.
    • Proceedings of the Korean Society for Technology of Plasticity Conference
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    • 2000.10a
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    • pp.185-190
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    • 2000
  • Die design by computer simulation has some advantages compared with the conventional method which has performed by designer's experiences and trials and errors. The die filling and solidification process of thixoforming process were simulated by MAGMAsoft/thixo module. First of all, thixoforming die design was applied to previously geometry shape. The value of pressure distribution shows high and uniform as the gate diameter is 18mm. Designed gating system considering the deformation of die and product was suggested by the filling simulation. Gate velocity(7.25m/s) of designed gating system shows that propriety to semi-solid metal working process and CAE results were in good agreement with experimental results.

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Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

  • Yang, Yil-Suk;Roh, Tae-Moon;Yeo, Soon-Il;Kwon, Woo-H.;Kim, Jong-Dae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.1
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    • pp.1-7
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    • 2009
  • This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

Robust Design of the Gate System for Flatness Improvement in Semi-Solid Casting Processes (반응고 주조공정에서 평면도 증대를 위한 게이트시스템의 강건설계)

  • Song, In-Ho;Chung, Sung-Chong
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.18 no.2
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    • pp.130-136
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    • 2009
  • Semi-solid casting(SSC) of magnesium alloys is increasingly being used to produce high quality components. This process is similar to the injection molding of plastics and is called thixomolding. Using this process, higher strength, thinner wall sections and tighter tolerances without porosity are obtained. The high strength and low weight characteristics of magnesium alloys render the high-precision fabrication of thin-walled components with large surface areas. They are widely used for the IT, auto and consumer electronics industries. However, warpage of the thin-walled sections degrade quality of the parts produced in the SCC process. To produce thin-walled magnesium alloy parts, the geometry of gating system on the quality of the finished products should be clearly studied. In this paper, to minimize warpage of the thin-walled sections, Taguchi method is applied to the optimal design of the gate geometry in the thixomolding process. Width, height, length and angle of the gating system are selected for the robust design parameters. Effectiveness of the robust design is verified through the CAE software.

An Automotive Radar Target Tracking System Design using ${\alpha}{\beta}$ Filter and NNPDA Algorithm (${\alpha}{\beta}$ 필터 및 NNPDA 알고리즘을 이용한 차량용 레이더 표적 추적 시스템 설계)

  • Bae, JunHyung;Hyun, EuGin;Lee, Jong-Hun
    • IEMEK Journal of Embedded Systems and Applications
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    • v.6 no.1
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    • pp.16-24
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    • 2011
  • Automotive Radar Systems are currently under development for various applications to increase accuracy and reliability. The target tracking is most important in single or multiple target environments for accuracy. The tracking algorithm provides smoothed and predicted data for target position and velocity(Doppler). To this end, the fixed gain filter(${\alpha}{\beta}$ filter, ${\alpha}{\beta}{\gamma}$ filter) and dynamic filter(Kalman filter, Singer-Kalman filter, etc) are commonly used. Gating is used to decide whether an observation is assigned to an existing track or new track. Gating algorithms are normally based on computing a statistical error distance between an observation and prediction. The data association takes the observation-to-track pairings that satisfied gating and determines which observation-to-track assignment will actually be made. For data association, NNPDA(Nearest Neighbor Probabilistic Data Association) algorithm is proposed. In this paper, we designed a target tracking system developed for an Automotive Radar System. We show the experimental results of the 77GHz FMCW radar sensor on the roads. Four tracking algorithms(${\alpha}{\beta}$ filter, ${\alpha}{\beta}{\gamma}$ filter, 2nd order Kalman filter, Singer-Kalman filter) have been compared and analyzed to evaluate the performance in test scenario.

Gated Clock-based Low-Power Technique based on RTL Synthesis (RTL 수준에서의 합성을 이용한 Gated Clock 기반의 Low-Power 기법)

  • Seo, Young-Ho;Park, Sung-Ho;Choi, Hyun-Joon;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.3
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    • pp.555-562
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    • 2008
  • In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

A Gating System Design to Reduce the Gas Porosity for Die Casting Mobile Device (다이캐스팅 모바일 기기의 기공결함 감소를 위한 유동구조 설계)

  • Jang, Jeong Hui;Kim, Jun Hyung;Han, Chul Ho
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.20 no.2
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    • pp.86-92
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    • 2021
  • Usually, the die-cast components used in small mobile devices require finishing processes, such as computer numerically controlled coating. In such cases, porosity is the most important defect. The shape of the molten aluminum that passes through the runner and gate in a mold is the one of the factors that influences gas porosity. To define the spurt index, which numerically indicates the shape of molten aluminum after the gate, Reynolds number and Ohnesorge number are used. Before die fabrication, computer-aided engineering analysis is performed to optimize the filling pattern. Finally, X-ray and surface inspection are performed after casting and machining to evaluate how the spurt index affects porosity and other product parameters. Based on the results obtained herein, a new gating system design process is suggested.

Design of Bio-signal Acquisition System in MRI Environment (MRI 내에서의 생체신호 측정 시스템 설계)

  • Jang, Bong-Ryeol;Park, Ho-Dong;Lee, Kyoung-Joung
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.871-872
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    • 2006
  • In this paper, we designed bio-signal acquisition system in Magnetic Resonance Imager(MRI) Environment. In MRI Environment, Strong RF Pulse and Gradient Field Switching Noise exist and can cause distortion of ECG. By this, ECG can lose their important information. So we proposed a bio-signal acquisition system with robust immunity to RF pulse and gradient switching noise. In conclusions, the proposed system showed the prevent saturation of measured biosignal and possibility of using cardiac gating and respiration gating method.

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Effect of Gate Number on the Characteristics of Interface between Cast and Forged Insert (게이트 수에 따른 단조형 인서트와 주물재 사이의 경계부 특성 분석)

  • Lee, S.M.;Yi, H.K.;Lee, G.Y.;Mun, S.M.;Moon, Y.H.
    • Journal of the Korean Society for Heat Treatment
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    • v.22 no.2
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    • pp.95-100
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    • 2009
  • In this study, the casting process using forged insert was investigated to characterize the manufacturing process by which good mechanical properties can be obtained when compared with existing casting products. Process analysis for the casting design was performed by using FVM (Finite Volume Method) software. In pouring process, three kinds of candidate gating systems are considered and analyzed respectively. The molten metal behavior in gating system is so important that it affects the solidification behavior of the cast. The results show that as the number of gates is increased, hardness of cast was increased and gaps of cast with forged insert were decreased.

Design of Low- Power Interface using Clock Gating Based on ODC Computation (ODC 클럭 게이팅을 이용한 저전력 Interface 회로설계)

  • Yang, Hyun-Mi;Kim, Hi-Seok
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.597-598
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    • 2008
  • In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

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Optimization of Casting Design for Automobile Transmission Gear Housing by 3D Filling and Solidification Simulation in Local Squeeze Diecasting Process (국부가압 다이캐스팅 공정에서 3차원 유동 및 응고해석을 통한 자동차 변속기 Gear Housing의 주조방안 설계 최적화)

  • Park, Jin-Young;Kim, Eok-Soo;Park, Yong-Ho;Park, Ik-Min
    • Korean Journal of Materials Research
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    • v.16 no.11
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    • pp.668-675
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    • 2006
  • In the partial squeeze casting process, the filling behavior of liquid metal and solidification pattern in thick area have significant influence on the quality of casting products and die life. For the optimal casting design of automobile transmission gear housing, various analyses were performed in this study by using computer simulation code, MAGMAsoft and the simulation results were compared and analyzed with experimental results. By air pressure criteria, internal porosities caused by air entrap during the mold filling were predicted and reduced remarkably by modification of gating system. Also, optimal squeeze-time lag to apply partial squeeze pin in thick area was calculated and the castings was free from shrinkage defects with the result of solidification analysis. Consequently, casting design for automobile transmission gear housing was optimized and approved by Computer Tomography.