• Title/Summary/Keyword: Gates Method

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Test Generation Algorithm for CMOS Circuits considering Time - skews (Time-stews를 고려한 CMOS회로의 테스트 생성 알고리즘)

  • Lee, C.W.;Han, S.B.;Kim, Y.H.;Jung, J.M.;Sun, S.K.;Lim, I.C.
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1551-1555
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    • 1987
  • This paper proposes a new test generation algorithm to detect stuck-open faults regardless of tine-skews in CMOS circuits. For testing for stuck-open faults regardless of time-skews, in this method, Hamming distance between the initialization pattern and the test pattern is made 1 by considering the responses of the internal gates. Therefore, procedure of the algorithm is simpler than that of the conventional methods because the line justification is unnecessary. Also, this method needs no extra hardware for testability and can be applied to random CMOS circuits in addition to two-level NAND - NAND CMOS circuits.

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FPGA implementation of A/D converter using stochastic logic (FPGA를 이용한 확률논리회로 A/D 컨버터의 구현)

  • 이정원;심덕선
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.847-850
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    • 1998
  • One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

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A Design of 8192-point FFT Processor using a new CBFP Scaling Method (새로운 CBFP 스케일링 방법을 적용한 8192점 FFT프로세서 설계)

  • 이승기;양대성;박광호;신경욱
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.113-116
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    • 2002
  • This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$. The SQNR of about 60-dB is achieved.

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사출성형의 게이트 위치 최적화

  • Lim, Won-Gil;Kim, Young-Il;Seol, Kwon
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1996.04a
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    • pp.787-791
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    • 1996
  • In injection molding, location of gates have great influence on the quality of plastic parts. Usually, they are located by releated trial and errors of experienced mold designers. In this topic we will present the numerical algorithm for finding the optimal gate locations. Optimization algorithm is devided into two stages. In the first stage, candidated optimal gate locations can be found by geometry of part only; whereas in the next step, more acculate gate locations are selected byiterative computation with optimization part and analysis part. So from the following study, we suggested the modified flow-volume method, which will define the optimal gate locations in injection mold design.

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Circuit Design of QAM Signal Mapper for Rotationally Invariant I/Q TCM (회전 불변 I/Q TCM을 위한 QAM 신호 사상기 회로 설계)

  • Kim, Chang-Joong;Lee, Ho-Kyoung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.49 no.1
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    • pp.26-30
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    • 2012
  • In this paper, we propose a signal generation method of rectangular QAM for rotationally invariant I/Q TCM. The proposed method consists of only digital logic gates without look-up table so that we can implement the system compactly. Our scheme can be applied to every rectangular QAM with the level higher than 64.

Look-up Table Based Pulse-Shaping Filter (Look-up 테이블 기반 펄스성형필터)

  • Lee, Chang-Ki;Lim, Hyung-Kyu
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.2
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    • pp.130-135
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    • 2009
  • In this paper, an efficient pulse-shaping filter structure for high-density and low-power electronic devices is proposed. The proposed structure is based on polyphase decomposition property and look-up table method. By Synopsys CAD simulations, it is shown that the use of the proposed method can result in reduction in the number of gates by 54% and can reduce power consumption by 9%.

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C-V Characteristics of Cobalt Polycide Gate formed by the SADS(Silicide As Diffusion Source) Method (SADS(Siliide As Diffusion Source)법으로 형성한 코발트 폴리사이트 게이트의 C-V특성)

  • 정연실;배규식
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.7
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    • pp.557-562
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    • 2000
  • 160nm thick amorphous Si and polycrystalline Si were each deposited on to 10nm thick SiO$_2$, Co monolayer and Co/Ti bilayer were sequentially evaporated to form Co-polycide. Then MOS capacitors were fabricated by BF$_2$ ion-implantation. The characteristics of the fabricated capacitor samples depending upon the drive-in annel conductions were measured to study the effects of thermal stability of CoSi$_2$and dopant redistribution on electrical properties of Co-polycide gates. Results for capacitors using Co/Ti bilayer and drive-in annealed at 80$0^{\circ}C$ for 20~40sec. showed excellent C-V characteristics of gate electrode.

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Virtual Prototyping of Area-Based Fast Image Stitching Algorithm

  • Mudragada, Lakshmi Kalyani;Lee, Kye-Shin;Kim, Byung-Gyu
    • Journal of Multimedia Information System
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    • v.6 no.1
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    • pp.7-14
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    • 2019
  • This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

A Establishment of Visual Component Elements and Investigation Analysis for a House-Gates in Rural Villages (농촌마을 주택대문의 경관구성요소 설정 및 실태파악 - 충남 청양군을 중심으로 -)

  • Lee, Gyeong-Jin;Cho, Soung-Ho;Song, Byeong-Hwa
    • Journal of Korean Society of Rural Planning
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    • v.13 no.3
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    • pp.83-90
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    • 2007
  • The purpose of main entrance was to protect the house with the wall and working for the house-gate where people come in and go out. On the other hand, the type of main entrance is changed variously depended on the materials for house and method of construction. Eleven villages in the Chungyang-Gun where the environment of rural villages is well maintained was chosen and researched to make data. These data of visual landscape elements were analysed by using the SPSS 12.0 for Windows. Relations of the visual component elements were analysed by the analysis for frequency and analysis for crosstab. From the above research we could conclude below results. Through review of the pre-researching and researching literatures, 11 types of visual component elements were selected such as the types of the gate, the looking through degree of the gate, the material of the gate, the color of the gate, the plan of the house, the material of the roof, a material of the wall, a color of the wall, the form of the penetration, the area to put, the area of a site, the year of the constructing a building. For the types of the gate, the gate from without the roof has been the most popular since it appeared 41.5%. For the looking through degree of the gate, a complete blockade form has been the most popular since it appeared 63.2%. For the material of the gate, the iron plate has been the most popular since it appeared 32.1%. For the color of the gate, color has been the most popular since it appeared 68.4%. For the plan of the house, 'ㄷ' form has beneath most popular since it appeared 38.3%. For the material of the roof. The Zinc has been the most popular since it appeared 51.9%. For a material of the wall, A cement mortar has been the most popular since it appeared 47.7%. For a color of the wall, Without tile color has hem the most popular since it appeared 67.0%. For the form of the penetration. The plain form has been the most popular since it appeared 54.0%. For tile area of a site, $100m^2{\sim}200m^2$ has been the most popular since it appeared 39.0%. The results of this study can provide to use of indicates four rural-housing reform. From now on, the results look forward to offering the meaning directions for the improvement of rural house gates.

A Study on the Method of Activation of Space of Gwangheemun Considering Historical and Cultural Speciality (역사·문화적 특수성을 고려한 광희문(光熙門)의 공간 활성화 방안 연구)

  • Kim, Ji Eun;Park, Eun Soo
    • Korea Science and Art Forum
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    • v.19
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    • pp.243-257
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    • 2015
  • The Cultural Heritage Administration has selected Seoul Fortress Wall as the representative heritage of Korea to be applied for being registered as UNESCO World Heritage and announced the plan to restore and organize it, which has increased the interest to the Seoul Fortress Wall, the Historical Site No. 10. The great work to make the heritage value of Walls, 4 Big Gates and 4 Small Gates composing the Seoul Fortress wall with the length of 18.627 km to be recognized worldwide has limits if it is focused only on the physical restoration. It is because the Seoul Fortress Wall represents the long historical and cultural value as the space of life which connects closely the capital city and its vicinity. We need the plan to discover and utilize historical and cultural contents of Seoul Fortress Wall and its vicinity. Especially, Gwangheemun, which is one of the four Small Gates of Seoul Fortress Wall, is a precious cultural heritage which represents the transition of fortification technology of Chosun period as the space representing ordinary people. However, now Gwangheemun and its vicinity does not stand out the charm because of passive accessibility, landscape falling behind and absence of program. This made the lack of domestic and overseas tourists and the convenient space and various contents. This reality is because the value of space has been considered simply as a cultural heritage without considering the traditional, historical and cultural specificity. Therefore, this study is aimed to find the meaning and value of Gwangheemun by discovering its own latent intangible cultural, historical and artistic resource, and to find the way to connect with Gwangheemun, the existing tangible traditional architectural space and the way of vitalizing Gwangheemun as a new space.