• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.411-414
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• 2014

A switch is one of the most useful circuits for controlling the path of signal transmission. It can be added to digital circuits to create a kind of gate-level device and it can also save information into memory. In RF subsystems, a switch is used in a different way than its general role in digital circuits. The most important characteristic to consider when designing an RF switch is keeping the isolation as high as possible while also keeping insertion loss as low as possible. For high isolation, we propose leakage signal cancellation and inductive switching for designing a singlepole double-throw (SPDT) RF switch. By using the proposed method, an isolation level of more than 23 dB can be achieved. Furthermore, the heterojunction bipolar transistor (HBT) process is used in the RF switch design to keep the insertion loss low. It is demonstrated that the proposed RF switch has an insertion loss of less than 2 dB. The RF switch operates from 1 to 8 GHz based on the $0.18-{\mu}m$ SiGe HBT process, taking up an area of $0.3mm^2$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.1-8
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• 1990

We made a 12-Laser Diode Array consisting of 12 Graded Index Separate Confinement (GRINSCH) InGaAs/Inp Buried Heterostructure 4 Quantum Well Laser Diodes and examined the potential of controlling lasing operation of each laser diode by the voltage to its electroabsorption region. Using Si V-Groove with 12 V-grooves, a 12-Laser Diode Array, and 12 optical fibers, we investigated the various characteristics of each laser diode by changing the voltage to its electro-absorption region. Finally, we thought over the promising way of implementing optical local area communication between electric circuit boards or between subscribers and a central office using a 12-Laser Diode Array, Si V-groove, and optical fibers.

• Journal of architectural history
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• v.24 no.3
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• pp.17-29
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• 2015

This study is about the change of multi-storied buildings in Hanyang, the capital city of Joseon Dynasty. The changes are divided into 3 phases in the viewpoint of architectural types and building types. The first phase is from the early Joseon Dynasty to the time of Japanese invasion to Korea and Sungryemun remains until now. The second phase is from 1592 to the the first half of the 18th century. Many multi-storied Buddhist halls were rebuilt at that time. In the final phase, many multi-storied gate buildings and multi-storied main buildings of palaces were rebuilt. And there are differences between the Buddhist buildings and the main buildings of palaces. By the way the change that architectural style of the Buddhist buildings and the main buildings of pal were switched and mixed occurred. For example, Anguksa Daeungjeon adopted the style of multi-storied gates and Injeongjeon adopted the style of multi-storied Buddhist halls. These phenomenon was result from periodical situation the monk carpenter and his disciple took part in governmental construction like Janganmun.

• The Journal of the Korea Contents Association
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• v.17 no.9
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• pp.32-38
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• 2017

In this study, we introduce a new way to improve the efficiency of Gait Analysis and promote its usage. This program can be shown in different points of view such as an individual or group patient data. The 'Gate Data Visualization Program' is improving its efficiency by minimizing the margin of error during research and promoting the easy interpretation. In addition, this program is designed to have an easy access, and can be used to develop the most basic medical equipment program to predict a probable disease for patient by collaborating with physicians specializing in neurosurgery.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1089-1094
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• 2013

In this study, we propose how th implement a MDDI(Mobile Display Digital Interface) protocol packet generation method in software. MDDI protocol is widely used in mobile display device. MDDI protocol packets are generated by software within micro processor. This method needs the minimum hardware configuration. In order to implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor are converted into LVDS signals, and transmitted by hardware within FPGA. This study suggests the benefits of the way how software can easily create a variety of packet. But, this proposed method takes more time in packet transmission compared to the traditional method. This weakness remains as a future challenge, which can be soon improved.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.2
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• pp.115-124
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• 2017

This paper aims to develop an SMPS topology for handling a high range of input voltages based on a DC-DC flyback converter circuit. For this purpose, 2 capacitors of the same specifications were serially connected on the input terminal side, with a flyback converter of the same circuit configuration serially connected to each of them, so as to achieve high input voltage and an effect of dividing input voltage. The serially connected flyback converters have the transformer turn ratio of 1:1, so that each coil is used for the winding of a single transformer, which is a characteristic of doubly-fed configuration and enables the correction of input capacitor voltage imbalance. In addition, a pulse transformer was designed and fabricated in a way that can achieve the isolation and noise robustness of the PWM output signal of the PWM controller that applies gate voltage to individual flyback converter switches. PSIM simulation was carried out to verify such a structure and confirm its feasibility, and a 100W class stack was fabricated and used to verify the feasibility of the proposed high voltage SMPS topology.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.9
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• pp.3266-3285
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• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.11
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• pp.4122-4144
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• 2021

In this fast-paced technological world, the Internet of Things is a ground breaking technology which finds an immense role in the present electronic world which includes different embedded sensors, devices and most other things which are connected to the Internet. The IoT devices are designed in a way that it helps to collect various forms of data from varied sources and transmit them in digitalized form. In modern era of IoT technology data security is a trending issue which greatly affects the confidentiality of important information. Keeping the issue in mind a novel light encryption strategy known as LCB is designed for IoT devices for optimal security. LCB exploits the benefits of Feistel structure and the architectural benefits of substitution permutation network both to give more security. Moreover, this newly designed technique is tested on (Virtex-7) XC7VX330T FPGA board and it takes much little area of 224 GE (Gate Equivalent) and is extremely fast with very less combinational path delay of 0.877 ns. An in-depth screening confirms the proposed work to promise more security to counter cryptographic attacks. Lastly the Avalanche Effect (AE) of LCB showed as 63.125% and 63.875% when key and plaintext (PT) are taken into consideration respectively.

• Journal of the Korean Society of Systems Engineering
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• v.17 no.2
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• pp.49-60
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• 2021

The Core Protection Calculator System (CPCS) is vital for plant safety as it ensures the required Specified Acceptance Fuel Design Limit (SAFDL) are not exceeded. The CPCS generates trip signals when Departure from Nucleate Boiling Ratio (DNBR) and Local Power Density (LPD) exceeds their predetermined setpoints. These setpoints are established based on the operating margin from the analysis that produces the SAFDL values. The goal of this research is to create a simplified CPCS that optimizes operating margin for I-SMRs. Because the I-SMR is compact in design, instrumentation placement is a challenge, as it is with Ex-core detectors and RCP instrumentation. The proposed CPCS addresses the issue of power flux measurement with In-Core Instrumentation (ICI), while flow measurement is handled with differential pressure transmitters between Steam Generators (SG). Simplification of CPCS is based on a Look-Up-Table (LUT) for determining the CEA groups' position. However, simplification brings approximations that result in a loss of operational margin, which necessitates compensation. Appropriate compensation is performed based on the result of analysis. FPGAs (Field Programmable Gate Arrays) are presented as a way to compensate for the inadequacies of current systems by providing faster execution speeds and a lower Common Cause Failure rate (CCF).