• Korean Journal of Human Ecology
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• v.3 no.2
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• pp.39-46
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• 2000

This research was to identify housing identity expressed on entrance features In Korean single detached houses. The data were collected from field study and content analysis method of 45 houses in Chonju city. The methods of observation, of measuring the size, of sketching. and of Photos of entrance feature in the single detached houses were used for this study. Results of this study were as follows. First. the height and the form both of main gate and of wall tended to be closed. In particular. the size of main gate tended to be shown off rather than having practical funtion. whereas the form of main gate were semi-opened and thus could not guaranteed privacy of the residents very well. Second, 53.3% of the direction of main entrance were found to be at right-an91e0 with main gate, which reflected the control needs of private life. Third. the balance of main gate and exterior was homogeneous, which expressed the increase of aethetic concern of exterior Finally. most of entrance approach were made of stones and bricks. This result indicated that the practical funtion of entrance approach was emphasized the emotional environment was not considered in building the entrance approach.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.972-973
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• 2007

Relationships between field effect mobility and grain size on pentacene thin-film transistors with $polyimide/SiO_2$ gate dielectrics have been studied. 6 kinds of polyimide were used as surface treatment gate dielectric layer. Grain size of the pentacene thin film were between 5 and $30\;{\mu}m$ and depended on the polyimide. The field effect mobility were also depended on the polyimide and the those values were from 0.027 to $0.69\;cm^2/(Vs)$. The field effect mobility tends to increase with increasing the grain size. Precursor type polyimide containing polyamic acid show better mobility of $0.69\;cm^2/(Vs)$ than soluble type polyimide. Bias stress characteristics in air are discussed in the basis of the grain size.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.99-102
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• 1999

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate signal delay, feed-through voltage and image sticking. To improve these problems which are caused by the fried-through voltage, we have evaluated new driving methods to reduce the fled-through voltage. Two level gate-pulse was used for the gate driving of the cst-on-common structure pixels. And two-gate line driving methods with the optimized gate signals were applied for the cst-on-gate structure pixels. These gate driving methods were better feed-through characteristics than conventional simple gate pulse. The evaluation of the suggested driving methods were performed by using a TFT-LCD array simulator PDAST which can simulate the gate, data and pixel voltages of a certain pixel at any time and at any location on a TFT array. The effect of the new driving method was effectively analyzed.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.120-126
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• 2006

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.367-372
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• 2006

A carbon nanotube field emission display(CNT FED) panel with a 2 inch diagonal size was fabricated using a screen printing of a prepared photo-sensitive CNT paste and vacuum in-line sealing technology. After a surface treatment of the patterned CNT, only the carbon nanotube tips are uniformly exposed on the surface. The diameter of the exposed CNTs are usually about 20 nm. Using the photo-sensitive CNT paste, we have developed a triode type CNT FEA with a self-aligned gate-emitter structure. The turn on voltage was around 100 V which corresponds to according the turn on field of about $40V/{\mu}m$. By the creation of a self-aligned gate-emitter structure, it is expected that the screen printed photo-sensitive CNT paste is promising as a good candidate for the large size field emission display.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.107-116
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• 1994

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

• Proceedings of the Korea Water Resources Association Conference
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• 2006.05a
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• pp.546-551
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• 2006

It considered the population decrease and becoming older in age of the Rural area and operates by unmaned-non power which self-controlled gate developed. The operational principal used a buoyancy and when water level in the canal arrived to the set water level, in order for gate to be opened. The plate in order to fix to the shape in the canal which begs, it did in the quadrilateral and the rainfall it is sour intensively, canal bank comfort plate in order to ascend completely, it designed. The result which establishes Self-controlled gate, the gate upstream 1km until degree there was water level synergistic effect. It developed 4 as the research project and it established in Ah San city, and it establishes the Self-controlled gate of $B3.2m{\times}H2.4m$ size in Damyang and 100ha it does water supply in the rice field.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.10
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• pp.713-719
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.970-973
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• 1999

When the size of the device is decreased, the hot carrier degradation presents a severe problem for long-term device reliability. In this paper we fabricated & tested the 0.26${\mu}{\textrm}{m}$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the characteristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve and charge trapping using the Hp4145 device tester As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially a hot carrier lifetime(nitride oxide gate device satisfied 30years, but the lifetime of wet gate oxide was only 0.1year), variation of Vg, charge to breakdown and charge trapping etc.