• 제목/요약/키워드: Gate position

검색결과 137건 처리시간 0.028초

회전식 수문의 중량 최소화에 대한 지지점 위치의 최적설계 (Optimal Location of Support Point for Weight Minimization in Radial Gate of Dam Structures)

  • 권영두;권순범;구남서;진승보
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2000년도 추계학술대회논문집A
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    • pp.492-497
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    • 2000
  • This paper focuses on the weight minimization of radial gate, as an extention of the previous work. Radial gates are commonly used to regulate the flow-rate of general purpose dams, due to its simplicity in manufacture and control. The present study identifies the optimum position of support point for 2 and 3 arm type radial gate, which guarantees the minimum weight satisfying strength constraint condition. These optimum designs are then compared with previously constructed radial gates. The results indicate that the weights of the optimized radial gates reduce by about 20%, compared to those of the conventionally designed radial gates.

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Extraction of Exact Layer Thickness of Ultra-thin Gate Dielectrics in Nanoscaled CMOS under Strong Inversion

  • Dey, Munmun;Chattopadhyay, Sanatan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권2호
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    • pp.100-106
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    • 2010
  • The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

설계영역 반복축소법에 의한 사출금형의 수지 유동균형을 위한 게이트 위치 최적화 (Optimization of Gate Location for Melt Flow Balancing in Injection Mold Cavity By Using Recursive Design Area Reduction Method)

  • 박종천;이규석;최성일;강진현
    • 한국기계가공학회지
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    • 제12권4호
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    • pp.114-122
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    • 2013
  • This study introduces an optimization methodology for the determination of gate location that ensures the melt flow balance within a part cavity of injection mold. A new sequential direct-search scheme based on the recursive reduction of the designer-specified gate design area is developed, and it is integrated with a commercial flow simulation tool for optimization. To quantify the level of melt flow balance, we employ the maximum difference among the fill times for the melt fronts to reach the boundary elements of part cavity as objective function. The proposed methodology is successfully applied in the case study of melt flow balancing in molding of a bar code scanner model. The result shows that the melt flow balance at the optimized gate positions is significantly improved from that for the initial gate position.

고무사출성형의 적정설계 (Optimum Design of Rubber Injection Molding Process)

  • 이은주;임광희;부타이지양
    • Korean Chemical Engineering Research
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    • 제49권1호
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    • pp.47-55
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    • 2011
  • K사의 고무 사출성형에 있어서 애로사항인 등속조인트 부트(boots)의 크 (crack) 발생 등의 문제점을 해결하기 위하여, 상용 CAE 프로그램인 MOLDFLOW(Ver. 5.2)를 이용한 전산모사를 수행하여 적정금형설계를 도출하고 적정작업조건을 구축하였다. 그 결과 크 의 발생 원인은 크 이 발생하는 위치에 형성되는 weld 및 meld line의 형성 때문이고, 또한 크 이 발생하는 위치에서의 가류(curing)가 불완전한 것이 확인되었다. 이와 같은 weld 및 meld line의 형성을 방지하기 위해서 게이트(gate)의 위치를 변경하고 최적위치에 설계함으로써, 유동선단(melt front)의 충돌 또는 수지흐름의 만남을 최소화하는 충전패턴(fill pattern)을 형성하고 부트 안쪽 하단의 크 발생을 방지하였다. Weld 및 meld line과 에어트랩(air trap) 불량이 가장 큰 게이트 위치는 각각 최적 게이트위치를 기준으로 서로 정반대 방향임이 관찰 되었다. 한편 몰드(mold)의 온도를 $170^{\circ}C$로 유지하게 함으로써 크 이 발생했던 위치에 가류조건을 만족시켰다.

충전과 상변화 현상을 포함한 주조과정에 대한 연구 (A Study of a Simultaneous Filling and Solidification During Casting Process)

  • 임익태;김우승
    • 대한기계학회논문집B
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    • 제23권8호
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    • pp.987-996
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    • 1999
  • An algorithm for modeling the filling of metal into a mold and solidification has been developed. This algorithm uses the implicit VOF method for a filling and a general implicit source-based method for solidification. The model for simultaneous filling and solidification is applied to the two-dimensional filling and solidification of a square cavity. The effects of the wall temperature and gate position on the solidification are examined. The mixed natural convection flow and residual flow resulting from the completion of a filling are included in this study to investigate the coupled effects of the filling and natural convection on solidification. Two different filling configurations (assisting flow and opposite flow due to the gate position) are analysed to study the effects of residual flow on solidification. The results clearly show the necessity to carry out a coupled filling and solidification analysis including the effect of natural convection.

LPR 시스템 트리거 신호 생성을 위한 딥러닝 슬라이딩 윈도우 방식의 객체 탐지 및 추적 (Deep-learning Sliding Window Based Object Detection and Tracking for Generating Trigger Signal of the LPR System)

  • 김진호
    • 디지털산업정보학회논문지
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    • 제17권4호
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    • pp.85-94
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    • 2021
  • The LPR system's trigger sensor makes problem occasionally due to the heave weight of vehicle or the obsolescence equipment. If we replace the hardware sensor to the deep-learning based software sensor in order to generate the trigger signal, LPR system maintenance would be a lot easier. In this paper we proposed the deep-learning sliding window based object detection and tracking algorithm for the LPR system's trigger signal generation. The gate passing vehicle's license plate recognition results are combined into the normal tracking algorithm to catch the position of the vehicle on the trigger line. The experimental results show that the deep learning sliding window based trigger signal generating performance was 100% for the gate passing vehicles including the 5.5% trigger signal position errors due to the minimum bounding box location errors in the vehicle detection process.

Implementation of Position Control of PMSM with FPGA

  • Reaugepattanawiwat, Chalermpol;Eawsakul, Nitipat;Watjanatepin, Napat;Pinprathomrat, Prasert;Desyoo, Phayung
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2004년도 ICCAS
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    • pp.1254-1258
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    • 2004
  • This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

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A Double-Hybrid Spread-Spectrum Technique for EMI Mitigation in DC-DC Switching Regulators

  • Dousoky, Gamal M.;Shoyama, Masahito;Ninomiya, Tamotsu
    • Journal of Power Electronics
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    • 제10권4호
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    • pp.342-350
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    • 2010
  • Randomizing the switching frequency (RSF) to reduce the electromagnetic interference (EMI) of switching power converters is a well-known technique that has been previously discussed. The randomized pulse position (RPP) technique, in which the switching frequency is kept fixed while the pulse position (the delay from the starting of the switching cycle to the turn-on instant within the cycle) is randomized, has been previously addressed in the literature for the same purpose. This paper presents a double-hybrid technique (DHB) for EMI reduction in dc-dc switching regulators. The proposed technique employed both the RSF and the RPP techniques. To effectively spread the conducted-noise frequency spectrum and at the same time attain a satisfactory output voltage quality, two parameters (switching frequency and pulse position) were randomized, and a third parameter (the duty ratio) was controlled by a digital compensator. Implementation was achieved using field programmable gate array (FPGA) technology, which is increasingly being adopted in industrial electronic applications. To evaluate the contribution of the proposed DHB technique, investigations were carried out for each basic PWM, RPP, RSF, and DHB technique. Then a comparison was made of the performances achieved. The experimentally investigated features include the effect of each technique on the common-mode, differential-mode, and total conducted-noise characteristics, and their influence on the converter’s output ripple voltage.

분황사 중문지 출토 치미 연구 (A Study on the Chimi Excavated from the Middle Gate Remains of Bunhwangsa Temple)

  • 김숙경
    • 건축역사연구
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    • 제26권5호
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    • pp.19-26
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    • 2017
  • This paper aimed to identify the architectural characteristics of the chimi excavated from ancient ruins, especially middle gate remains of Bunhwangsa Temple in the Unified Silla period. Middle gate had planned $3{\times}2$ with 295mm measuring unit and gabled building. Detailed study of the shape of chimi of the middle gate restored by related field experts reveals as follows. 1) Height of chimi is 4.5(130.6cm) of Tang's system of measurement classified as large one. 2) The front and back side square hole is made for transverse timber placement. 3) Position of chimi is not the end of the ridge of roof, it moved toward the center. 4) Construction method of chimi is structured with smaller beam and center column. 5) Width and height of the ridge is less than 38cm and 54cm to be approximately, Width and height of the gabled ridge is less than 38cm and 50cm. 6) This chimi is considered to be very unique when compared to existing ancient restored chimis, it is designed to be advantageous to the chimi construction.

Aluminium Gate를 적용한 4H-SiC MOSFET의 Design parameter에 따른 전기적 특성 분석 (Electrical characterization of 4H-SiC MOSFET with aluminum gate according to design parameters)

  • 백승환;이정민;서우열;구용서
    • 전기전자학회논문지
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    • 제27권4호
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    • pp.630-635
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    • 2023
  • SiC는 고온, 고전압을 비롯한 악조건에서의 내성이 기존 산업분야의 대다수를 점유하고 있는 Silicon에 비해 우수하여 전력반도체 분야에서 Silicon의 위치를 대체하여 가고 있다. 본 논문은 전력 반도체 소자 중 하나인 4H-SiC Planar MOSFET에 알루미늄으로 Gate를 형성하여 다결정 Si 게이트와 대비, 파라미터 값들이 일관성을 갖도록 하였으며, SiC MOSFET의 채널 도핑 농도에 변화를 주어 문턱전압과 항복전압, IV 특성을 연구하였다.