• 제목/요약/키워드: Gate line

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5-MeV Proton-irradiation characteristics of AlGaN/GaN - on-Si HEMTs with various Schottky metal gates

  • Cho, Heehyeong;Kim, Hyungtak
    • Journal of IKEEE
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    • v.22 no.2
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    • pp.484-487
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    • 2018
  • 5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

A Study on the Analysis of Traffic Distribution and Traffic Pattern on Traffic Route using ND-K-S (ND-K-S를 적용한 항로 통항분포와 통항패턴 분석에 관한 연구)

  • Kim, Jong-Kwan
    • Journal of Navigation and Port Research
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    • v.42 no.6
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    • pp.446-452
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    • 2018
  • A traffic route is an area associated with high risk for accidents due to the flow of heavy traffic. Despite this concern, most studies related to traffic focus solely on traffic distribution. Therefore, there is a need for studies investigating the characteristics of ships' routes and traffic patterns. In this study, an investigation was carried out to analyze the traffic distribution and pattern in 3 major traffic routes for 3 days. For the purpose of the study, based on the prevailing traffic conditions, the route was divided into 10 gate lines. The ships passing through the lines were also classified into either small, medium and large. ND-K-S (normal distribution, kurtosis, and skewness) test was carried out for the traffic distribution at each gate line based on the information analyzed on each traffic route. The analysis of the results obtained from the ND test showed that large vessels have normal distribution, medium sized vessels have satisfied normal distribution in one-way route only while small sized vessels do not have normal distribution. According to the result obtained from the K-S test, normal traffic pattern shows a significant difference between two-way route and one-way route. Results obtained from the K test result shows that in the case of one-way route, vessels have a traffic pattern using a wide range on traffic route. Further analysis shows that vessels concentrate on one side of route in case of two-way route. Results obtained from the S test show that, in case of one-way route, vessels have a normal traffic pattern according to center line. However, analysis pf the results shows that vessels are shifted to the right side of route in case of two-way route. Despite these findings, it should be noted that this study was carried out in only 3 ports, therefore there is need for investigation to be carried out in various routes and conditions in future studies.

Minimizing the Average Distance of Separated Points on the Plane in the L1-Distance

  • Kim, Jae-Hoon
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.1-4
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    • 2012
  • Given separated points divided by a line, called a wall, in a plane, we aim to make a gate in the wall to connect the separated points to each other. In this setting, the problem is to find a location for the gate that minimizes the average distance between the points. The problem is a variant of the well-known facility location problem, which is extensively studied in the fields of operations research, location theory, theoretical computer science, and so on. In this paper, we consider the $L^1$-distance of the points in the plane. The points are projected onto the wall and so the problem is transformed to a proximity problem of points on a line. Then it is shown that the transformed problem is related to the weighted median problem of points on the line. Therefore, we obtain an O(n log n)-time algorithm to solve our problem.

A Study of Ceramic Injection Molding of Watch Case Composed of $ZrO_2$ Powder

  • Kwak, T.S.
    • Proceedings of the Korean Powder Metallurgy Institute Conference
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    • 2006.09a
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    • pp.505-506
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    • 2006
  • This study is focused on the manufacturing technique of powder injection molding of watch case made from zirconia powder. A series of computer simulation processes were applied to the prediction of the flow pattern in the inside of the mould and defects as weld-line. The material properties of melted feedstock, including the PVT graph and thermal viscosity flowage properties were measured to obtain the input data to be used in a computer simulation. Also, a molding experiment was conducted and the results of the experiment showed a good agreement with the simulation results for flow pattern and weld line location. On the other hand, gravity and inertia effects have an influence on the velocity of the melt front because of the high density of ceramic powder particles during powder injection molding in comparison with polymer's injection molding process. In the experiment, the position of the melt front was compared with the upper gate and lower gate positions. The gravity and inertia effect could be confirmed in the experimental results.

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Electrochemical Characteristics of AIZr Thin Film for TFT-LCD Bus Line (TFT-LCD 버스선을 위한 AIZr 합금 박막의 전기 .화학적 특성에 관한 연구)

  • 김장권;김동식;이종호;정관수
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.49-52
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    • 2001
  • The electrochemical characteristics of Alalloy thin film with low impurity concentrations AIZr deposited by using do magnetron co-sputtering deposition are investigated for the applications as gate bus line in the TFT-LCD panel. AlZr thin films were deposited various atomic percent of Zr. For increasing Zr atomic percent the hillock density was decreased and the resistivity was increased. The deposited thin films show the decrease of resistivity and the increase of grain size after the RTA at 300 $^{\circ}C$for 20 min.. Moreover, the resistivity of AIZr does not show appreciable grain size dependence after RTA. It is concluded that the decrease of resistivity after RTA is due to the increase of grain size. The annealed AIZr(at.0.9%) is found to be hillock free. The electrode potentials of AIZr were less than ITO's (-1.4V) and the etching rate of AIZr(at.0.9%) was 3.8587ng/sec. in KOH(10%) solution. Caculation results reveal that the AIZr(at.0.9%) thin film can be applicable to gate line of 25" UXGA class TFT-LCD panels and can not be applicable to data line.line.

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Design of Graphic Memory for QVGA-Scale LCD Driver IC (QVGA급 LCD Driver IC의 그래픽 메모리 설계)

  • Kim, Hak-Yun;Cha, Sang-Rok;Lee, Bo-Sun;Jeong, Yong-Cheol;Choi, Ho-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.12
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    • pp.31-38
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    • 2010
  • This paper presents the design of a graphic memory for QVGA-scale LCD Driver IC (LDI). The graphic memory is designed based on the pseudo-SHAM for the purpose of small area, and the memory cell structure is designed using a bit line partitioning method to improve sensing characteristics and drivabilties in the line-read operation. Also, a collision protection circuit using C-gate is designed to control collisions between read/write operations and self-refresh/line-read operations effectively. The graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and the operations of the graphic memory have been verified using Hspice. The results show that the bit-bitb line voltage difference, ${\Delta}V$ increases by 40%, the charge sharing time between bit and bitb voltages $T_{CHGSH}$ decreases by 30%, and the current during line-read decreases by 40%.

Validation Study for Image Performance of I-131 Using GATE Simulation Program (GATE 시뮬레이션 프로그램을 이용한 I-131의 영상 특성의 타당성에 관한 연구)

  • Baek, Cheol-Ha;Kim, Dae Ho;Lee, Yong-Gu;Lee, Youngjin
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.5
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    • pp.133-137
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    • 2017
  • The purpose of this study was to validate for GATE (Geant4 Application for Tomographic Emission) simulation by comparing the results of GATE simulation and experiment in real SPECT system. Futhermore, we want to prove that it is possible that the quantitative research of gamma camera/SPECT imaging for therapeutic radio isotope by using GATE simulation. In this study, the SPECT system on simulation referred to the parameters of Stream-R Forte version 1.2 (Philips Medical System, Best and Heerlen, Netherlands). To understand the I-131 image of gamma camera/SPECT system, we acquired the energy spectrum and measured the full width at half maximum (FWHM) which comes from line spread function (LSF) with and without scatter material in real SPECT system. And to compare with experiment, we also measured the FWHM and acquired the energy spectrum without scatter material in GATE simulation. As a result, without scatter material, the energy peak was almost same location, which are located nearby 364 keV, and other spectrum factors are same tendency in both cases. The FWHM was increased by increasing the distance of source to detector, and the error rate was approximately 3.8%. When we used the line source with scatter material, energy spectrum also indicated similar tendency in both cases. As you confirmed earlier, GATE simulation included real instrument and radioisotope characters for therapeutic radioisotope. Therefore this result that it was possible that various quantitative study for therapeutic radioisotope imaging in gamma camera/SPECT using GATE simulation.

Suppression of Gate Oxide Degradation for MOS Devices Using Deuterium Ion Implantation Method

  • Lee, Jae-Sung
    • Transactions on Electrical and Electronic Materials
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    • v.13 no.4
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    • pp.188-191
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    • 2012
  • This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

Fabrication of CNT FEA Self-aligned between Gate and Emitter using Screen Printing Method (스크린 프린팅 방법에 의해 게이트-에미터간 자체정렬된 3극 구조의 CNT FEA 제조)

  • Kwon, Sang-Jik
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.4
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    • pp.367-372
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    • 2006
  • A carbon nanotube field emission display(CNT FED) panel with a 2 inch diagonal size was fabricated using a screen printing of a prepared photo-sensitive CNT paste and vacuum in-line sealing technology. After a surface treatment of the patterned CNT, only the carbon nanotube tips are uniformly exposed on the surface. The diameter of the exposed CNTs are usually about 20 nm. Using the photo-sensitive CNT paste, we have developed a triode type CNT FEA with a self-aligned gate-emitter structure. The turn on voltage was around 100 V which corresponds to according the turn on field of about $40V/{\mu}m$. By the creation of a self-aligned gate-emitter structure, it is expected that the screen printed photo-sensitive CNT paste is promising as a good candidate for the large size field emission display.

Array Simulation Characteristics and TFT-LCD Pixel Design Optimization for Large Size, High Quality Display (대면적 고화질의 TFT-LCD 화소 설계 최적화 및 어레이 시뮬레이션 특성)

  • 이영삼;윤영준;정순신;최종선
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.11a
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    • pp.137-140
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    • 1998
  • An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate si후미 distortion and pixel charging capability. which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio and level-shift of the pixel voltage were simulated with varying the parameters. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

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