• Journal of Ocean Engineering and Technology
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• v.28 no.2
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• pp.160-166
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• 2014

Because of industrial development, industrial facilities are becoming more complex and diversified. Plant industries are focused on productivity improvement, cost reduction, and product uniformity by simplifying production processes using automated control. Furthermore, plant industries require higher pressures and temperatures to improve energy efficiency. For this reason, the valves used in plants are operated under harsh conditions. Globe valves and gate valves are mainly used for high pressure these days. However, these valves have various problems, including low maintainability and high cost, due to structural problems. Therefore, butterfly and ball valve applications are increasing in industrial plants. This paper suggests a quadruple-offset butterfly valve that is applicable to bi-direction use, and the principle design parameters are suggested. The selected design parameters are an eccentric flange center line and shaft centerline(Offset 1), an eccentric seat centerline and disc shaft centerline(Offset 2), the angle between the flange centerline and seat wedge angle(Offset 3), the angle between the vertical direction of the disc shaft centerline and seat centerline(Offset 4), and the seat engagement angle. To analyze the interaction effect of the design parameters, ANOM and ANOVA were performed with an orthogonal array. The parameters were found to have effects in the following order: Offset 2, Offset 1, engagement angle, Offset 3, and Offset 4. The interaction between the parameters was insignificant.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.409-412
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• 2002

The LNA(Low Noise Amplifier) is designed for use in low cost commercial application covered fully IMT-2000 band(1920~2170MHz, BW=250MHz). It is optimized source inductance for source lead and designed to equivalent etched line. The LNA uses a high pass impedance matching network for noise match and simple structure. The bias circuit designs have been made self-biased with a negative voltage applied to gate. The power supply voltage is 8V, total current is 180mA. The LNA is biased at a Vgs of -0.4, Vds of 4V for first stage and Vds of 5V for second stage. The LNA is designed competitively for commercial product specification. The measured gain and noise figure of the completed amplifier was 20dB and 1dB, respectively. Also, input VSWR, P1dB and gain flatness was measured of 1.14 ~ l.3dB, 22.4dBm and $\pm$0.45dB, respectively. The designed LNA can be used for commercial product.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.10
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• pp.4865-4885
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• 2019

We propose a FPGA based design that performs real-time power-efficient analysis of heterogeneous sensor data using adaptive ANN on edge gateway of smart military wearables. In this work, four independent ANN classifiers are developed with optimum topologies. Out of which human activity, BP and toxic gas classifier are multiclass and ECG classifier is binary. These classifiers are later integrated into a single adaptive ANN hardware with a select line(s) that switches the hardware architecture as per the sensor type. Five versions of adaptive ANN with different precisions have been synthesized into IP cores. These IP cores are implemented and tested on Xilinx Artix-7 FPGA using Microblaze test system and LabVIEW based sensor simulators. The hardware analysis shows that the adaptive ANN even with 8-bit precision is the most efficient IP core in terms of hardware resource utilization and power consumption without compromising much on classification accuracy. This IP core requires only 31 microseconds for classification by consuming only 12 milliwatts of power. The proposed adaptive ANN design saves 61% to 97% of different FPGA resources and 44% of power as compared with the independent implementations. In addition, 96.87% to 98.75% of data throughput reduction is achieved by this edge gateway.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.298-305
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• 2003

In this paper, we proposed a high performance lookup controller for IP packet forwarding engine of ATM based label edge routers. The lookup controller is designed to provide services such as MPLS, VPN, ELL, and RT services as well as the best effort. For high speed searching for IP addresses, we employed a TCAM based hardware search device not using traditional algorithmic approaches. We also implement lookup control functions into FPGA for fast processing of packet header and lookup control. The proposed lookup controller is designed to support differenciated services for users and to process in pipelined mechanism for performance improvement. A two-step search scheme is also applied to perform lookup for the key combined with multi-field of packet header. We found that the proposed lookup controller provides the performance of about 16M packets per second through simulations.

• Journal of the Korean Institute of Rural Architecture
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• v.17 no.3
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• pp.11-18
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• 2015

This study is aimed to clarify the transitional characteristics of old roads and alleys lasting more than 100 years(1915-2015) in traditional urban area(Seongan-dong) of cheongju, historic inland and castle city of Korea. Cheongju castle had been completely destroyed In 1915, and urban structures been also altered last 100 years from 2015 now. Periodically, after destruction of castle, existing roads were extended and transformed to straight line for connecting with around. Expanding urban area to all directions of castle boundary in 1930-40s, town planning were created. These projects were completed in 1960-70s, the street network was built as they are. Since the 1980s, changes had been occurred in the details such as an extension of the unexecuted roads, the opening of fire lane in a block, and etc. In change and construction of roads, urban district plan in 1939 and reorganization since 1967 were planned and established with the type, location, and width of the large, medium and small roads based on data before destruction of castle. Except the width of 25m Sajikro(large3-1) and Sangdangro(large3-8,9,10), the width of 15m Namsaro(medium2-1) and Namjuro (medium2-4) as an extension of the roads, the other roads were small roads equivalent to the existing roads, and so remain intact figure of streetscape. As such, roads of east-west and north-south cross type, roads showing the outline of Cheongju castle fortress, and alleys outside the south gate are sustained in Seongan-dong of cheongju as historic urban area, and also present roads are delicately executed to the existing urban fabric.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1729-1750
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• 2018

Voltage source inverters (VSIs) are widely used to drive induction motors in industry applications. The quality of output waveforms depends on the switching sequences used in pulse width modulation (PWM). In this work, all existing optimal space vector pulse width modulation (SVPWM) switching strategies are studied. The performance of existing SVPWM switching strategies is optimized to realize a tradeoff between quality of output waveforms and switching losses. This study generalizes the existing optimal switching sequences for total harmonic distortions (THDs) and switching losses for different modulation indexes and reference angles with a parameter called quality factor. This factor provides a common platform in which the THDs and switching losses of different SVPWM techniques can be compared. The optimal spatial distribution of each sequence is derived on the basis of the quality factor to minimize harmonic current distortions and switching losses in a sector; the result is the minimum ripple loss SVPWM (MRSLPWM). By employing the sequences from optimized switching maps, the proposed method can simultaneously reduce THDs and switching losses. Two hybrid SVPWM techniques are proposed to reduce line current distortions and switching losses in motor drives. The proposed hybrid SVPWM strategies are MRSLPWM 30 and MRSLPWM 90. With a low-cost PIC microcontroller (PIC18F452), the proposed hybrid SVPWM techniques and the quality of output waveforms are experimentally validated on a 2 kVA VSI based on a three-phase two-level insulated gate bipolar transistor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• Journal of the Korean Physical Society
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• v.73 no.11
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• pp.1764-1773
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• 2018

A-PET is a quad-head PET scanner developed for use in small-animal imaging. The dimensions of its volumetric field of view (FOV) are $46.1{\times}46.1{\times}46.1mm^3$ and the gap between the detector modules has been minimized in order to provide a highly sensitive system. However, such a small FOV together with the quad-head geometry causes image quality degradation. The main factor related to image degradation for the quad-head PET is the mispositioning of events caused by the penetration effect in the detector. In this paper, we propose a precise method for modelling the system at the high spatial resolution of the A-PET using a LOR (line of response) based ML-EM (maximum likelihood expectation maximization) that allows for penetration effects. The proposed system model provides the detection probability of every possible ray-path via crystal sampling methods. For the ray-path sampling, the sub-LORs are defined by connecting the sampling points of the crystal pair. We incorporate the detection probability of each sub-LOR into the model by calculating the penetration effect. For comparison, we used a standard LOR-based model and a Monte Carlo-based modeling approach, and evaluated the reconstructed images using both the National Electrical Manufacturers Association NU 4-2008 standards and the Geant4 Application for Tomographic Emission simulation toolkit (GATE). An average full width at half maximum (FWHM) at different locations of 1.77 mm and 1.79 mm are obtained using the proposed system model and standard LOR system model, which does not include penetration effects, respectively. The standard deviation of the uniform region in the NEMA image quality phantom is 2.14% for the proposed method and 14.3% for the LOR system model, indicating that the proposed model out-performs the standard LOR-based model.

• Journal of IKEEE
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• v.26 no.2
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• pp.313-318
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• 2022

The feedback voltage detection structure is proposed to alleviate overshoot and undershoot caused by the removal of the existing external output capacitor. Conventional LDO regulators suffer from overshoot and undershoot caused by imbalances in the power supply voltage. Therefore, the proposed LDO is designed to have a more improved transient response to form a new control path while maintaining only the feedback path of the conventional LDO regulator. A new control path detects overshoot and undershoot events in the output stage. Accordingly, the operation speed of the pass element is improved by charging and discharging the current of the gate node of the pass element. LDO regulators with feedback voltage sensing architecture operate over an input voltage range of 3.3V to 4.5V and have a load current of up to 200mA at an output voltage of 3V. According to the simulation result, when the load current is 200mA, it is 73mV under the undershoot condition and 61mV under the overshoot condition.