• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.312-320
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• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of Power Electronics
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• v.9 no.3
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• pp.464-471
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• 2009

This paper introduces a new Motion-$SPM^{TM}$ (Smart Power Modules) module in Single In-line Package (SIP), which is a fully optimized intelligent integrated IGBT inverter module for up to 1kW low power motor drive applications. This module offers a sophisticated, integrated solution and tremendous design flexibility. It also takes advantage of pliability for the arrangement of heat-sink due to two types of lead forms. It comes to be realized by employing non-punch-through (NPT) IGBT with a fast recovery diode and highly integrated building block, which features built-in HVICs and a gate driver that offers more simplicity and compactness leading to reduced costs and high reliability of the entire system. This module also provides technical advantages such as the optimized cost effective thermal performances through IMS (Insulated Metal Substrate), the high latch immunity. This paper provides an overall description of the Motion-$SPM^{TM}$ in SIP as well as actual application issues such as electrical characteristics, thermal performance, circuit configurations and power ratings.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.71-73
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• 2000

최근 고 에너지 저장 및 발생장치의 개발은 군사용에서 산업용으로 응용되면서 각종 첨단 설비가 개발되고 있다. 본 논문에서는 전자빔 발생기로 쓰이는 Gyroklystron용 대전력, 고전압, 전류 펄스 전원장치로 입력부, 특고압 발생부, 고압 정류부 및 IGBT 펄스 스위치 구성하고 그 설계 및 개발 자료에 대하여 기술하였다. 대전력 고전압 전류펄스 전원장치를 위한 각 구성 부분의 제어 및 설계 특징은 다음과 같다. 입력부인 IGBT Inverter는 펄스 전원장치의 제어를 위하여 출력 고전압을 Feedbark System에 의해 펄스 설정 전압을 유지하도록 제어하며, 또한 펄스 출력중에 직류 고전압부의 전압강하, 즉 펄스 진압의 Drop이 커지는 것을 방지하기 위하여 Fast Dynamics를 갖도록 Feedback System을 구성하였다. 단상 특고압 승압용 변압기 3대를 직렬접속한 특고압 발생부는 PWM 제어된 전압을 입력받아 특고압으로 승압시키며 고압 펄스성 전압과 매우 높은 dV/dt 전압이 인가되므로 Stray Capacitance가 최소가 되어야 하며 절연파괴로부터 보호될 수 있어야 한다. 고압 정류부는 Inverter와 특고압 변압기에 의하여 전원이 공급되므로 교류전압의 교번 순간에 매우 높은 전압변동률을 가지는 Fast Recovery High Voltage Rectifier로 설계 제작되어졌다. 펄스 스위치인 IGBT 스위치는 Gate Driver에 의해 구동되어 지며 주어진 펄스 사양을 만족시키게 된다. 특히 소자의 전압특성을 고려하여 120KV의 전압 값을 갖도록 설계, 제작하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.62-68
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• 1989

In this paper, Analog/Digital BCDMOS technology that the bipolar devices for driver applications CMOS devices for logic applications, and DMOS devices for high voltage applications is pressented. An optimized poly-gate p-well CMOS process is chosen to fabricate the BCDMOS, and the basic concepts to desigh these devices are to improve the characteristics of bipolar, CMOS & DMOS with simple process technology. As the results, $h_{FE}$ value is 320 (Ib-$10{\mu}A$ for bipolar npn transistor, and there is no short channel effects for CMOS devices which have Leff to $1.25{\mu}m$ and $1.35{\mu}m$ for n-channel and p-channel, respectively. Finally, breakdown voltage is obtained higher than 115V for DMOS device.

• ETRI Journal
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• v.37 no.6
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• pp.1165-1175
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• 2015

This paper presents an advanced sensorless permanent magnet (PM) brushless motor controller integrated circuit (IC) employing an automatic lead-angle compensator. The proposed IC is composed of not only a sensorless sine-wave motor controller but also an isolated gate-driver and current self-sensing circuit. The fabricated IC operates in sensorless mode using a position estimator based on a sliding mode observer and an open-loop start-up. For high efficiency PM brushless motor driving, an automatic lead-angle control algorithm is employed, which improves the efficiency of a PM brushless motor system by tracking the minimum copper loss under various load and speed conditions. The fabricated IC is evaluated experimentally using a commercial 200 W PM brushless motor and power switches. The proposed IC is successfully operated without any additional sensors, and the proposed algorithm maintains the minimum current and maximum system efficiency under $0N{\cdot}m$ to $0.8N{\cdot}m$ load conditions. The proposed IC is a feasible sensorless speed controller for various applications with a wide range of load and speed conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.612-615
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• 2013

Hub BLDC(Brushless Direct Current) motor, called wheel-in motor is a outer rotor type high efficient direct driving motor which have a multi-pole permanent magnet type rotor as a driving wheel. This study shows a hub BLDC motor speed controller design methode using PIC micro controller to drive 2 wheels or 3 wheels driving body having hub motor driving shaft. The motor driver unit consists of six discrete MOSFET switching devices and the gate driving module is directly designed for high economy.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.19-26
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• 2016

In this study, a bidirectional DC-DC converter for idle stop and go (ISG) is developed to reduce fuel consumption. A three-phase non-isolated half-bridge converter is selected through a design method by considering efficiency and volume. According to the state of charge of the batteries at both the low-voltage and high-voltage sides, buck mode, which charges a low-voltage battery from the generated motor energy, and boost mode, which provides power to the motor from the low- and high-voltage battery sides, are required in the ISG system. Hence, an autonomous and seamless bidirectional control method using a variable current limiter is proposed for mode change. A 1.8 kW engineering sample of the proposed converter has been built and tested to verify the validity of the proposed concept. The maximum efficiencies, including gate driver and control circuit losses, are 96.4% in charging mode and 96.1% in discharging mode.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1309-1311
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• 2000

본 논문에서는 입력부, 특고압 발생부 및 고압 정류부, IGBT Pulse Switch로 구성된 Gyro-klystron용 대전력, 고전압, 전류 펄스 전원장치의 설계 및 개발에 대하여 기술하였다. 대전력, 고전압, 전류 펄스 전원장치를 위한 각 구성부분의 제어 및 설계 특징은 다음과 같다. 입력부인 IGBT Inverter는 펄스 전원장치의 전압 제어를 위하여 출력 고전압을 Feedback System 제어에 의해 Pulse 설정 전압을 갖도록 제어하며, 또한 Pulse 출력중에 직류 고전압부의 전압강하, 즉 Pulse 전압의 Drop이 커지는 것을 방지하기 위하여 Fast Dynamics를 갖도록 Feedback System을 구성하였다. 3대의 단상 특고압 승압변압기가 직렬로 구성된 특고압 발생부는 PWM된 전압을 입력받아 특고압으로 승압시킨다. 특고압 변압기는 고압 Pulse성 전압과 매우 높은 dV/dt 전압이 인가되므로 Stray Capacitance가 최소가 되어야 하며 절연파괴로부터 보호될 수 있어야 한다. 고압 정류부는 Inverter와 특고압변압기에 의하여 전원이 공급되므로 교류전압의 교번순간에 매우 높은 전압 변동률을 가지는 Fast Recovery High Voltage Rectifier로 설계, 제작되어졌다. Pulse Switch인 IGBT Switch는 Gate Driver에 의해 구동되어 진다. 주어진 Pulse 사양을 만족시키며 특히 소자의 전압 특성을 고려하여 120KV의 전압값을 갖도록 설계, 제작하였다. 본 논문에서는 고전압 펄스 전원장치 각 부분의 설계에 대하여 기본적인 사항들을 제시하며, 실험결과를 통하여 제안된 방식의 우수한 특성을 입증한다.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.