• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.659-665
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• 2017

In this paper, a low complexity fast Fourier transform(FFT) processor is proposed for multiple input multiple output(MIMO) systems. The IEEE 802.11ac standard has been adopted along with the demand for a system capable of high channel capacity and Gbps transmission in order to utilize various multimedia services using a wireless LAN. The proposed scalable FFT processor can support the variable length of 64, 128, 256, and 512 for 8x8 antenna configuration as specified in IEEE 802.11ac standard with MIMO-OFDM scheme. By reducing the required number of non-trivial multipliers with mixed-radix(MR) and multipath delay commutator(MDC) architecture, the complexity of the proposed FFT processor was dramatically decreased. Implementation results show that the proposed FFT processor can reduced the logic gate count by 50%, compared with the radix-2 SDF FFT processor. Also, compared with the 8-channel MR-2/2/2/4/2/4/2 MDC processor and 8-channel MR-2/2/2/8/8 MDC processor, it is shown that the gate count is reduced by 18% and 17% respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.379-379
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• 2013

본 논문에서는 Normal ink jetting 공법으로 OTFT를 제작할 때 coffee stain effect에 의해서 반도체 소자의 특성이 저하되는 것을 극복하기 위해서 동일한 위치에 동일한 부피로 Droplet을 형성하는 Multiple ink jetting 공법을 통해 TIPS pentacene 결정의 Morphology와 전기적 특성이 어떻게 변화하는지 알아 보았다. Multiple ink jetting의 drop 횟수가 증가할수록 coffee stain effect에 의해서 형성된 가운데 영역의 Dendrite grain이 점점 작아지다가 7 Drops 이후로는 Big grain 만 남게 되었다. Active layer의 표면 Roughness는 drop 횟수가 증가할수록 낮아지다가 일정 count 이후로는 다시 높아지는 것을 확인할 수 있었다. 전계 이동도(mobility)는 drop 횟수가 증가할수록 커지다가 일정 count 이후로는 saturation되는 것을 확인할 수 있었다. Multiple ink jetting에 의해서 만들어진 OTFT 소자의 전계 이동도(mobility)는 1 drop과 10 drops에서 각각 0.0059, 0.036 cm2/Vs 로 6배 정도 차이가 있었다. 이것은 첫 drop에 의해 만들어진 가운데 Dendrite grain 영역이 Multiple ink jetting을 반복하면서 점점 작아지게 되어 사라지고 두꺼운 Grain 영역만 남게 된 것으로 판단된다. Vth 와 On/Off ratio는 1 drop과 10 drops에서 각각 -3 V, -2 V 그리고 $3.3{\times}10^3$, $1.0{\times}10^4$를 보였다. OTFT의 substrate로 Flexible한 polyethersulfone (PES) 기판을 사용하였고, 절연체로 Spin coating된 Poly-4-vinylphenol (PVP)가 사용되었으며, Gate 및 Source/Drain 전극은 Au를 50 nm 두께로 증착하였다. Channel의 width와 length는 각각 100 um, 40 um 였고, Gate 전극 위에 Active layer를 형성한 Bottom gate 구조로 제작되었다. Ink jet으로 제작된 TIPS pentacene의 결정성은 x-ray diffraction (XRD)와 광학 현미경으로 분석하였고 Thickness profile은 알파스텝 측정기를 이용하였으며, OTFT의 전기적 특성은 Keithley-4,200을 사용하여 측정하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.228-231
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• 1999

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

• ETRI Journal
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• v.34 no.2
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• pp.284-287
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• 2012

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.3
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• pp.148-151
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• 2017

This research concerns field rings for 3.3kV planar gate power insulated-gate bipolar transistors (IGBTs). We design an optimal field ring for a 3.3kV power IGBT and analyze its electrical characteristics according to field ring parameters. Based on this background, we obtained 3.3kV high breakdown voltage and a 2.9V on state voltage drop. To obtain high breakdown voltage, we confirmed that the field ring count was 23, and we obtained optimal parameters. The gap distance between field rings $13{\mu}m$ and the field ring width was $5{\mu}m$. This design technology will be adapted to field stop IGBTs and super junction IGBTs. The thyristor device for a power conversion switch will be replaced with a super high voltage power IGBT.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.15-24
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• 1998

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.118-123
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• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.