• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1355-1357
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• 2005

This paper discusses Gate-driver circuit for improved switching characteristics. This resonant gate-driver recycles the energy stored in the gate capacitance to reduce the turn-off switching loss associated with a conventional gate-driver. Reducing the loss reduces the power consumption and hence the subsequent power dissipation in the resonant gate-driver. The design considerations of implementing a practical MOSFET gate-driver using this topology are discussed.

• 한국전기전자재료학회논문지
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• 제32권5호
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• pp.361-365
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• 2019

Although there is no strict definition of a power semiconductor device, a general description is a semiconductor that has capability to control more than 1 W of electricity. Integrated gate bipolar transistors (IGBTs), which are power semiconductors, are widely used in voltage ranges above 300 V and are especially popular in high-efficiency, high-speed power systems. In this paper, the size of the gate was adjusted to test the variation in the yield voltage characteristics by measuring the electric field concentration under the trench gate. After the experiment Synopsys' TCAD was used to analyze the efficiency of threshold voltage, on-state voltage drop, and breakdown voltage by measuring the P- region and its size under the gate.

• 조명전기설비학회논문지
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• 제19권6호
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• pp.9-15
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• 2005

본 연구는 새로 고안된 부정-논리곱 논리기능을 가지는 방전 논리 게이트 플라즈마 디스플레이 패널의 논리 게이트 방전특성을 해석한 것이다. 이 방전 논리 게이트는 방전 경로에 따른 전극사이의 전압을 제어하여 논리 출력을 유도한다. 실험결과 논리 게이트의 방전특성은 두 수직전극에 인가되는 전압들의 상호관계에 영향을 받는다는 것을 알았다. 그리고 대화면 PDP에의 적용 가능성을 검토하기 위하여 전극의 선저항에 의한 방전특성을 평가한 결과, 두 수직전극들의 선저항에 의한 전압강하가 논리 게이트의 방전에 미치는 영향은 미미한 것으로 추론되었다. 실험을 통해 방전 논리 게이트를 구성하는 각 전극들의 펄스전압과 전류제한저항의 최적 값들을 구하였으며 49[V]의 최대동작마진을 얻었다.

• 한국전기전자재료학회논문지
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• 제36권6호
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• pp.609-613
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• 2023

In this paper, a 1,200 V Si-based IGBT used in electric vehicles and new energy industries was designed. A field stop IGBT with a separate gate structure, which is the proposed structure, was designed to change trench depth and split gate width variables. Then, the general trench structure and electrical characteristics were compared and analyzed. As a result of conducting the trench depth experiment, it was confirmed that the breakdown voltage was the highest at 6 ㎛, and the on-state voltage drop was the lowest at 3.5 ㎛. In the separate gate width experiment, it was confirmed that the breakdown voltage decreased as the variable increased, and the on-state voltage drop increased. Therefore, it may be seen that it is preferable not to change the width of the separate gate. In addition, experiments show that there is no difference in on-state voltage drop compared to a structure in which a general field stop structure has a separate gate structure. In other words, it is determined that adding a dummy gate with a separate gate structure to the active cell will significantly improve the on-voltage drop characteristics, while confirming that the on-voltage drop does not change, and while having excellent characteristics in terms of breakdown voltage.

• 한국전기전자재료학회논문지
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• 제33권4호
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• pp.281-285
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• 2020

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

• 한국전기전자재료학회논문지
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• 제24권8호
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• pp.609-615
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• 2011

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.

• 대한전기학회논문지
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• 제35권7호
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• pp.278-284
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• 1986

Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bias shows both positive and negative resistance characteristics depending on the gate threshold voltage and gate-to source bias votage. In this paper, the decision method of the gate crossover voltage by the temperature variation and a new method to determine the gate threshold voltage graphecally are presented.

• 한국전기전자재료학회논문지
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• 제17권8호
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• pp.799-805
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• 2004

Two dimensional MEDICI simulator is used to study the characteristics of latch-up current of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics, latch-up current density, ON-voltage drop and electrical property with the variations of p-base impurity concentrations. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have the better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer p-base structure under the floating $N^+$ emitter indicates to have the better characteristics of latch-up current and breakover voltage.

• 전자공학회논문지A
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• 제33A권2호
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• pp.131-139
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• 1996

Inthis apper wa analyzed the channel-hot-electron programming characteristics of the single-poly EEPROM with different control gate and drain structures. The single-poly EEPROM uses the p$^{+}$/n$^{+}$-diffusion in the n-well as a control gate instead of the second poly-silicon. The program and erase characteristics of the single-poly EEPROM were verified using the two-dimensional device simulator, MEDICI. The single-poly EEPROM was fabricated using 0.8$\mu$m ASIC CMOS process, and its CHE programming characteristics were measured using HP4155 parameteric analyzer and HP8110 pulse gnerator. Especially we investigated the CHE programming characteristics of the single-poly EEPROM with the p$^{+}$-diffusion or n$^{+}$-diffusion in the n-well as a control gate and the LDD or single-drain structure. The single-poly EEPROM with p$^{+}$-diffusion in the n-well as a control gate and single-drain structure was programmed to about VT$\thickapprox$5V with VDS=6V, VCG=12V(1ms pulse width).th).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.