• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.536-540
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• 1999

We have developed a refractory WNx self-aligned gate GaAs metal-semiconductor field-effect transistor(MESFET) using $SiO_2$ side-wall process. The MESFET hasa fully ion-implanted, planar, symmetric self-alignment structure, and it is quite suitable for integration. The uniform trans-conductance of 354nS/mm up to Vgs=+0.6V and the saturation current of 171mA/mm were obtained. As high as 43GHz of cut-off frequency hs been realized without any de-embedding of parasitic effects. The refractory WNx self-aligned gate GaAs MESFET technology is one of the most promising candidates for realizing linear power amplifier ICs and multifunction monolithic ICs for use in the digital mobile communication systems such as hand-held phone(HHP), personal communication system (PCS) and wireless local loop(WLL).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.71-78
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• 1994

We have developed GaAs power metal semiconductor field effect transistors (MESFETs) for 4.7V operation under 900 MHz using a low-high deped structures grown by molecular beam epitaxy (MBE). The fabricted MESFETs with a gate widty of 7.5 mm and a gate length of 1.0.mu.m show a saturated drain current (Idss) of 1.7A and an uniform transconductance (Gm) of around 600mS, for gate bias ranged from -2.4 V to 0.5 V. The gate-drain breakdown voltage is measured to be higher than 25 V. The measured rf characteristics of the MESFETs at a frequency of 900 MHz are the output power of 31.4 dBm and the power added efficiency of 63% at a drain bias of 4.7 V.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.101-104
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• 2008

Too high stress of the bottom Mo layer of the gate line is thought to be the main reason for H-line mura. H-Line mura is eliminated effectively by changing the gate line metal structure from Mo/AlNd/Mo to AlNd/Mo. The new structure does not influence the panel's electrical characteristics.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1119-1122
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• 2005

A selective deposition of Co thin films for thin film transistor gate electrode has been carried out by the growth with combination of micro-contact printing and metal organic chemical vapor deposition (MOCVD). This results in the elimination of optical lithography process. MOCVD has been employed to selectively deposit Co films on preformed OTS gate pattern by using micro-contact printing (${\mu}CP$). A hydrogenated amorphous silicon TFT with a Co gate selectively formed on SAMs patterned structure exhibited a subthreshold slope of 0.88V/dec, and mobility of $0.35cm^2/V-s$, on/off current ratio of $10^6$, and a threshold voltage of 2.5V, and thus demonstrating the successful application of the novel bottom-up approach into the fabrication of a-Si:H TFTs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.185-192
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• 1995

In this study, very fine photoresist pattern was examined using the image reversal process. And very fine photoriesist pattern (less than 0.2um) was obtsined by optimizing the exposure and reversal baking condition of photoresist. The produced pattern does not show the loss of thickness, and has a sparp negative edge profile. also, the ion implanted 0.25um T-shaped gate MESFET was fabricated using this resist pattern and the directional evaporation of gate metal. The fabricated MESFET has the maximum transconductance of 302 mS/mm, and the threshold voltage of -1.8V, and the drain saturation current of this MESFET was 191 mA/mm.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.64.1-64.1
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• 2012

Next generation displays such as high performance LCD, AMOLED, flexible display and transparent display require specific TFT back-planes. For high performance TFT back-planes, low temperature poly silicon (LTPS), and metal-oxide semiconductors are studied. Flexible TFT backplanes require low temperature processible organic semiconductors. Not only development of active semiconducting materials but also design and synthesis of semiconductor corresponding gate dielectric materials are important issues in those display back-planes. In this study, we investigate the high heat resistant polymeric gate dielectric materials for organic TFT and inorganic TFT with good insulating properties and processing chemical resistance. We also controlled and optimized surface energy and morphology of gate dielectric layers for direct printing process with solution processible organic and inorganic semiconductors.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.212-216
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• 2004

In this paper, we have fabricated a triode field emitter using carbon nanotubes (CNTs) directly grown by thermal chemical vapor deposition(CVD) method as an electron omission source. Vertically aligned CNTs have been grown in the center of the gate hole, to the size of 1.5 ${\mu}{\textrm}{m}$ in diameter, with help of a sacrificial layer of a type generally used in metal tip process. By the method of tilling the substrate, we made CNTs emitters both with and without SiO$_2$layer, a sidewall protector, deposited on sidewall of gate. After that we researched the electrical characteristics about two types of emitters. In effect, a sidewall protector can enhance the electrical characteristics by suppressing the problem of short circuits between the gate and the CNTs. The leakage current of an emitter with a sidewall protector is approximately sevenfold lower than that of an emitter without it at a gate voltage of 100 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.212-212
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• 2013

We fabricate and characterize top gate Graphene transistor using aluminum oxide as a gate insulator by atomic layer deposition (ALD). It is found that due to absence of functional group and dangling bonds, ALD of metal oxide is difficult on Graphene. Here we used 4-mercaptopheneol as a functionalization layer on Graphene to facilitate uniform oxide coverage. Contact angle measurement and Atomic force microscopy were used to confirm uniform oxide coverage on Graphene. Raman spectroscopy revealed that functionalization with 4-mercaptopheneol does not induce any defect peak on Graphene. Our device shows mobility values of 4,000 $cm^2/Vs$ at room temperature which also suggest top gate stack does not significantly increase scattering. The noncovalent functionalization method is non-destructive and can be used to grow ultra-thin dielectric for future Graphene applications.

• Korean Journal of Materials Research
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• v.3 no.6
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• pp.638-644
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• 1993

The degradation of dielectric breakdown field of 8nm-thick gate oxide ($SiO_2$) for Tipolycide MOS(meta1-oxide-semiconductor) capacitor with different annealing conditions and thickness of the polysilicon film on gate oxide was investigated. The degree of degradation in dielectric breakdown strength of the gate oxide for Ti-polycide gate became more severe with increasing annealing temperature and time, especially, for the case that thickness of the polysilicon film remained on the gate oxide after silicidation was reduced. The gate oxide degradation may be occurred by annealing although there is no direct contact of Ti-silicide with gate oxide. From SIMS analysis, it was confirmed that the degration of gate oxide during annealing was due to the diffusion of titanium atoms into the gate oxide film through polysilicon from the titanium silicide film.