• 한국초전도ㆍ저온공학회논문지
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• 제21권1호
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• pp.6-9
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• 2019

Developing a gate-tunable, scalable, and topologically-protectable supercurrent qubit and integrating it into a quantum circuit are crucial for applications in the fields of quantum information technology and topological phenomena. Here we propose that the nano-hybrid supercurrent transistors, a superconducting quantum analogue of a transistor, made of topological insulator nanowire would be a promising platform for unprecedented control of both the supercurrent magnitude and the current-phase relation by applying a voltage on a gate electrode. We believe that our experimental design will help probing Majorana state in topological insulator nanowire and establishing a solid-state platform for topological supercurrent qubit.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.92-92
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• 2009

본 논문에서는 strained Silicon-on-Insulator (sSOI) 기판에 제작된 triple-gate MOSFETs 의 이동도와 단채널 효과에 대하여 분석 하였다. Strained 실리콘에 제작된 소자는 전류의 방향이 <110> 밤항일 경우 전자의 이동도는 증가하나 정공의 이동도는 오히려 감소하는 문제점이 있다. 이를 극복하기 위하여 소자에서 전류의 방향이 <110>방향에서 45 도 회전된 <100> 방향으로 흐르게 제작하였다. Strain이 가해지지 않은 기판에 제작된 동일한 구조의 소자와 비교하여 sSOI 에 제작된 소자에서 전자의 이동도는 약 40% 정공의 이동도는 약 50% 증가하였다. 채널 길이가 100 nm 내외로 감소함에 따라 나타나는 drain induced barrier lowering (DIBL) 현상, subthreshold slope (SS)의 증가 현상에서 sSOI에 제작된 소자가 상대적으로 우수한 특성을 보였으며 off-current leakage ($I_{off}$) 특성도 sSOI기판이 더 우수한 특성을 보였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권12호
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• pp.755-760
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• 1999

Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1434-1435
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• 2006

본 연구에서는 polymer gate insulators에 따른 pentacene 유기 박막 트랜지스터 (Organic Thin-Film Transistors)의 전기적 특성을 atom force microscope (AFM), x-ray diffraction (XRD) 그리고 I-V 측정을 이용하여 분석하였다. Pentacene 박막 트랜지스터의 전기적 특성은 pentacene의 증착 조건뿐만 아니라 polymer gate insulator에 따라 크게 영향을 받는다. 따라서 다양한 polymer 기판 위에 온도, 두께 그리고 증착 속도에 따라 pentacene을 증착 하였다. 그리고 증착된 pentacne을 AFM, XRD를 이용하여 pentacene의 구조, 결정화 그리고 grain 크기 등을 분석하였다. 또한 inverted stagger며 구조의 pentacene 박막 트랜지스터 소자를 제작하고 I-V 측정하여 그 결과를 분석하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1315-1318
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• 2007

Hafnium dioxide nano film as gate insulator for organic thin film transistors is prepared by atomic layer deposition. Mostly crystalline of $HfO_2$ films can be obtained with oxygen plasma and with water at relatively low temperature of $150^{\circ}C$. $HfO_2$ was deposited as a uniform rate $1.2A^{\circ}/cycle$. The morphology and performances of OTFT will be discussed.

• 한국전자파학회논문지
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• 제14권6호
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• pp.648-654
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• 2003

본 논문에서는 비 산화물인 불소화합물 게이트절면막을 이용하여 박막반도체 다이아몬드 MS계면(Metal-Insulator-Semiconductor Interface)의 전기적 안정화를 실현하였다. 특히 산소 게터링 효과(Oxygen-Gettering Effect)에 의한 표면준위 억제를 통해, 박막반도체 다이아몬드 MIS계면에 있어서 최적의 전기적 특성을 부여하는 BiF2 게이트절연막을 개발하였다. 본 논문의 결과에 의하면, BaF$_2$ 게이트 절연막을 이용하여 제작한 A1/BaF2/diamond MIS 다이오드와 MISFET(Metal-Insulator-Semiconductor Field Effect Transistor)로부터 저농도의 ~10101/$\textrm{cm}^2$ eV의 표면준위밀도가 관측되었고, 그리고 이제까지 발표된 다이아몬드 박막반도_체 FET중 최고치인 400 $\textrm{cm}^2$/Vs의 유효이동도가 관찰되었다.

• Journal of Information Display
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• 제11권3호
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• pp.113-118
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• 2010

The effect of hydrogen in the alumina gate insulator on the bottom gate oxide thin film transistor (TFT) with an InGaZnO film as the active layer was investigated. TFT with more H-containing alumina films (TFT A) fabricated via atomic layer deposition using a water precursor showed higher stability under positive and negative bias stresses than that with less H-containing alumina deposited using ozone (TFT B). While TFT A was affected by the pre-vacuum annealing of GI, which resulted in $V_{th}$ instability under NBS, TFT B did not show a difference after the pre-vacuum annealing of GI. All the TFTs showed negative-bias-enhanced photo instability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.185-190
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• 2003

In this paper, it was demonstrated that the organic thin film transistors were fabricated by the organic gate insulators with vapor deposition polymerization (VDP) processing. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and 2,2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride (6FDA) and ODA, and cured at $150^{\circ}C$ for 1hr. Electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure obtained to the saturated slop in the saturation region and the subthreshold non-linearity in the triode region. Field effect mobility, threshold voltage, and on-off current ratio in $0.45\;{\mu}m$ thick gate dielectric layer were about $0.17\;cm^2/Vs$, -7 V, and $10^6\;A/A$, respectively. Details on the explanation of compared to organic thin-film transistors (OTFTS) electrical characteristics of ODPA-ODA and 6FDA-ODA as gate insulators by fabricated thermal co-deposition method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1146-1149
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• 2006

In this study, nanocomposite layer composed of PMMA-co-MMA and $TiO_2$ was prepared by sol-gel process using TTIP as a precursor and was utilized as a gate insulator of OTFTs. The composite insulator provides the lower threshold voltage and the enhanced sub threshold slope of OTFTs mainly due to its higher dielectric constant than that of the bare PMMA-co-MMA. Consequently, it is demonstrated that the sol-gel process can open an interesting direction for the fabrication of high-performance OTFTs, and contribute for OTFTs to be feasible for real applications.