• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2011년도 제42회 하계학술대회
• /
• pp.1700-1701
• /
• 2011

본 논문에서는 게이트 절연막인 poly(4-vinylphenol) (PVP) 용제 농도 변화에 따른 유기 박막 트랜지스터를 제작하고 그 특성을 분석하였다. PVP는 propylene glycol monomethyl ether acetate(PGMEA) 와 poly melamine-co-formaldehyde (CLA)를 혼합하여 cross linked PVP를 만들어 사용하였다. Cross-liked PVP의 CLA 농도 비율을 각각 6 wt%, 9 wt%로 변화시켜 유기 박막 트랜지스터를 제작하고 소자의 전기적 특성을 분석 하였다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
• /
• pp.1305-1307
• /
• 2007

We show that the electrical properties of organic thinfilm transistors(OTFTs) can be enhanced by controlling the morphology of interface between screen printed electrodes and gate dielectrics. Modified surface of the insulator layer($SiO_2$) affect on the interface energy of electrode on $SiO_2$ layer. Contact angle measurement and FT-IR spectrum shows that the interface is properly modified. OTFTs device with high efficiency has been realized through modification of interface layer.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
• /
• pp.622-625
• /
• 2003

The dependence of stress-induced leakage current on LTPS TFTs was characterized in this study. The impacts of poly-Si crystallization, gate insulator, impurity activation, hydrogenation process and electrostatic discharge damage were investigated. It was observed more TFTs instable characteristic under those process-assisted processes. According to the LTPS roadmap, smaller geometric and low temperature process were the future trend and the stress-induced leakage current should be worthy of remark.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
• /
• pp.1081-1084
• /
• 2003

Structural morphology, annealing behavior and dielectric properties of polyaniline-emeraldine base (Pani-EB) and poly methyl methacrylate (PMMA) thin films prepared by spin coating technique have been studied. MIM and MISM structures were used to investigate annealing and dielectric behavior. The XRD and AFM spectrum of as grown and annealed thin films indicates the amorphous nature. The observed amorphous phase, low loss, dielectric behavior and thermal stability even at high temperatures implies the feasibility of utilizing PMMA and Pani-EB thin films as gate dielectric insulator layer in organic thin film transistors which can find application in flat panel display.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 A
• /
• pp.250-255
• /
• 2000

본 "수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구"를 통해 수소플라즈마 전처리 공정에 의한 실리콘 기판 표면의 활성화를 통해 실리콘 직접 접합 공정을 수행하여 접합된 기판쌍을 제작할 수 있었으며, 접합된 기판쌍에 대한 CMP(Chemical Mechanical Polishing) 공정을 통해 SOI(Silicon on Insulator) 기판을 제작할 수 있었다. 아울러, 소자의 동작 시뮬레이션을 통해 기존 SOI LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자에 비해 동작 특성이 향상된 이중 채널 SOI LIGBT 소자의 설계 파라미터를 도출하였으며, 공정 시뮬레이션을 통해 소자 제작 공정 조건을 확립하였고, 마스크 설계 및 소자 제작을 통해 본 연구 수행으로 개발된 SOI 기판의 전력용 반도체 소자 제작에 대한 가능성을 확인할 수 있었다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.355-355
• /
• 2010

We studied the dependence of the performance of schottky barrier metal-oxide-field effect transistors(SB MOSFETs) on the work function of source/drain metals. A strong impact of the various work functions and the light wavelengths on the transistor characteristics is found and explained using experimental data. We used an insulator of a high thickness (100nm) and back gate issues in SOI substrate, subthreshold swing was measured to 300~400[mV/dec] comparing with a ideal subthreshold swing of 60[mV/dec]. Excellent characteristics of Al/Si was demonstrated higher on/off current ratios of ${\sim}10^7$ than others. In addition, extensive photoresponse analysis has been performed using halogen and deuterium light sources(200<$\lambda$<2000nm).

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.367-367
• /
• 2010

Electrical characteristics of Large-grain silicon with Ni-induced crystallization which gate insulator is made of 80 nm $SiO_2$ and 20 nm SiNx was fabricated and measured with different channel widths, channel length fixed $10{\mu}m$. Focusing on the changes of channel widths from $4{\mu}m$ to $40{\mu}m$. Field-effect mobility decreased from 111.30 to $94.10\;cm^2/V_s$ when the channel widths increased. Still threshold voltage was almost similar with -1.06V.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.89-90
• /
• 2008

본 연구에서는 PECVD(Plasma Enhanced CVD) 에서 사용하는 유해 가스인 $SiH_4$ 대신에 유기 사일렌 반응 물질인 TEOS(Tetraethyl Orthosilicate, Si$(OC_2H_5)_4)$를 이용하여 상압 화학 기상 증착법 (Atmospheric Pressure CVD, APCVD)으로 실리콘 산화막을 증착하고 박막의 조성과 특성 및 화학적, 전기적 특성들을 살펴보았다. TEOS 반응원료를 이용한 CVD 공정에서 공정 온도를 낮추기 위한 방법으로 강력한 산화제인 오존을 이용하여 공정온도를 $400^{\circ}C$이하로 낮췄으며, 유리기판 상의 ELA(Excimer Laser Annealing)처리된 다결정 실리콘 기판에 트랜지스터 소자를 제작하고, 게이트 절연막으로의 전기적 특성을 살펴보았다.

• 한국전기전자재료학회논문지
• /
• 제21권8호
• /
• pp.711-714
• /
• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.185-188
• /
• 2001

In this study, $Al_2$O$_3$films have been deposited with Atomic Layer Deposition(ALD) for gate insulator for MPTMA and $H_2O$ at low temperature below 40$0^{\circ}C$ . Conventional methods of $Al_2$O$_3$thin film deposition have suffered from the poor step coverage due to reduction of device dimension and increasing contact/via hole aspect ratio. ALD is a self-limiting growth process with controlled surface reaction where the growth rate is only dependent on the number of growth cycle and the lattice parameter of materials. ALD growth process has many advantages including accurate thickness control, large area and large batch capability, good uniformity, and pinholes freeness.