• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.35-39
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• 2009

A novel Helmholtz coil inductively coupled plasma(H-ICP) etcher is proposed and characterized for deep nano-scale CMOS technology. Various hardware tests are performed while varying key parameters such as distance between the top and bottom coils, the distance between the chamber ceiling and the wafer, and the chamber height in order to determine the optimal design of the chamber and optimal process conditions. The uniformity was significantly improved by applying the optimum conditions. The plasma density obtained with the H-ICP source was about $5{\times}10^{11}/cm^3$, and the electron temperature was about 2-3 eV. The etching selectivity for the poly-silicon gate versus the ultra-thin gate oxide was 482:1 at 10 sccm of $HeO_2$. The proposed H-ICP was successfully applied to form multiple 60-nm poly-silicon gate layers.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.2014-2020
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• 2017

A compact current model applicable to both single-gate (SG) and double-gate (DG) tunneling field-effect transistors (TFETs) is presented. The model is based on Kane's band-to-band tunneling (BTBT) model. In this model, the well-known and previously-reported quasi-2-D solution of Poisson's equation is used for the surface potential and length of the tunneling path in the tunneling region. An analytical tunneling current expression is derived from expressions of derivatives of local electric field and surface potential with respect to tunneling direction. The previously reported correction factor with three fitting parameters, compensating for superlinear onset and saturation current with drain voltage, is used. Simulation results of the proposed TFET model are compared with those from a technology computer-aided-design (TCAD) simulator, and good agreement in all operational bias is demonstrated. The proposed SG/DG-TFET model is developed with Verilog-A for circuit simulation. A TFET inverter is simulated with the Verilog-A SG/DG-TFET model in the circuit simulator; the model exhibits typical inverter characteristics, thereby confirming its effectiveness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2004.05a
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• pp.159-165
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• 2004

The shrinkages of injection molded parts are different in molding operational conditions and mold design. It also differs from resins. The shrinkages of injection molded parts for PBT (polybutylene terephthalate), PC (polycarbonate),and glass reinforced PBT and PC have been studied for various operational conditions of injection molding. The part shrinkage of crystalline polymer, PBT was higher than that of amorphous polymer, PC by about two times. The part shrinkages of both polymers decreased as glass fiber content increases. Higher Injection temperature and lower injection pressure resulted in a higher shrinkage in both PBT and PC resins. As mold temperature increases the part shrinkage of PC decreased. However, the part shrinkage of PBT increased as mold temperature increases. The part shrinkage of both PBT and PC resins decreased as gate size increases since the pressure delivery is mush easier for a larger gate size. The part shrinkage of flow direction was less than that of the perpendicular direction to the flow for both pure and glass fiber reinforced resins. The part shrinkage at the position close to the gate was less than that of the position far from the gate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.462-470
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• 2015

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from $10^{\circ}$ to $20^{\circ}$ is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.36-42
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials with all non-zero coefficients over finite field GF($P^m$). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of $(m+1)^2$ identical cells, each cell consists of one mod(p) additional gate and one mod(p) multiplicative gate. Proposed multiplier need one mod(p) multiplicative gate delay time and m mod(p) additional gate delay time not clock. Also, our architecture is regular and possesses the property of modularity, therefore well-suited for VLSI implementation.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.707-710
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• 2002

A 120kV/70A high voltage switch has been installed at Korea Atomic Energy Research Institute in Taejon to supply power with Korea Superconducting Tokamak Advanced Research (KSTAR) Neutral Beam Injection (NBI) system. NBI system requires fast cutoff of the power supply voltage for protection of the grid when arc detected and fast turn-on the voltage for sustaining the beam current. Therefore the high voltage switch and arc current detection circuit are important part of the NBI power supply and there are much need for high voltage solid state switches in NBI system and a broad area of applications. This switch consisted of 100 series connected MOSFETs and adopted the proposed simple and reliable gate drive circuit without bias supply, Various results taken during the commissioning phase with a 100kW resistive load and NBI source are shown. This paper presents the detailed design of 120kV/70A high voltage MOSFETs switch and simple gate drive circuit. Problems with the high voltage switch and gate driver and solutions are also presented.

• Journal of the Korean Institute of Landscape Architecture
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• v.27 no.1
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• pp.110-121
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• 1999

The purpose of this study is to focus on the characteristics of the form and preference of the main gates of universities. The gate of a university have both functions and artistic design aspects. Fifty-two universities selected for this study were placed all around country except for Je-ju island. The following two research methods were used for this study. 1) an analysis of form character through a classification of the types. 2) and analysis of preference to the gates through a side show. The results are summarized as follows: 1. Main gates of universities were classified by covered-type and uncovered-type in existence of cover. And they were classified by eighteen types in detail. 2. Visual preference have been analyed by using the regression, the result is as follows: Y=-0.357+0.630 X$_4$+0.377X$_1$+0.075X$_2$-0.015X$_3$($R^2$=0.971, X$_4$;harmony, X $_1$;speciality, X$_2$;softness, X$_3$;complex) 3. The gate of Chung-Ang university(Ahn Sung campus) is the highest of all the universities at the average of preference 4.32 through result of slide show. Covered type has a higher preference than uncovered type. This has a good modification and decoration in front side type of main gate.

• Transactions of Materials Processing
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• v.13 no.6 s.70
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• pp.515-521
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• 2004

The shrinkages of injection molded parts are different in molding operational conditions and mold design. It also differs from resins. The shrinkages of injection molded parts fur PBT (polybutylene terephthalate), PC (polycarbonate), and glass reinforced PBT and PC have been studied for various operational conditions of injection molding. The part shrinkage of crystalline polymer, PBT was higher than that of amorphous polymer, PC by about two times. The part shrinkages of both polymers decreased as glass fiber content increases. Higher injection temperature and lower injection pressure resulted in a higher shrinkage in both PBT and PC resins. As mold temperature increases the part shrinkage of PC decreased. However, the part shrinkage of PBT increased as mold temperature increases. The part shrinkages of PBT and PC resins decreased as gate size increases since the pressure delivery is mush easier for a larger gate size. The part shrinkage of flow direction was less than that of the perpendicular direction to the flow for both pure and glass fiber reinforced resins. The part shrinkage at the position close to the gate was less than that of the position far from the gate.

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.2
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• pp.7-16
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• 2019

Neural networks can be implemented in variety of ways, and specialized chips is being developed for hardware improvement. In order to apply such neural networks to wearable devices, the compactness and the low power operation are essential. In this point of view, a suitable implementation method is a digital circuit design using field programmable gate array (FPGA). To implement this system, the learning algorithm which takes up a large part in neural networks must be implemented within FPGA for better performance. In this paper, a back propagation algorithm among various learning algorithms is implemented using FPGA, and this neural network is verified by OR gate operation. In addition, it is confirmed that this neural network can be used to analyze various users' bio signal measurement results by learning algorithm.