• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Nuclear Engineering and Technology
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• v.50 no.5
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• pp.780-787
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• 2018

This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• Progress in Superconductivity and Cryogenics
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• v.5 no.1
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• pp.44-47
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• 2003

There are several simulation programs in studying superconductor RSFQ (Rapid Single flux Quantum) electronic devices, which include WRspice, WinS, PSCAN, and JSIM. Even though different research groups use different simulation programs, it is not well known about which program gives the simulation results closer to the measurement values. In this work, we used both WRspice and WinS to simulate RSFQ OR gate and to compare the results from the different simulations. This comparison would help in deciding which program is better in the RSFQ circuit design. In the confluence buffer, which is the one of the main components of the DR gate, the measured bias margins were ${\times}23.2%$, while the margins from the simulations were ${\pm}35.56%$ from WRspice and it 53.1% from WinS. However, with the actual fabricated circuit parameters WRspice gave ${\pm}27%$. In WinS the circuit did not operate. We concluded that WRspice is more reliable.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.509-520
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• 1992

AIGaAs /GaAs HBT OR /NOR gate. which can be used for high speed digital system was designed. Equivalent circuit parameters of HBT were obtained from Gummel-Poon's model and direct extraction method. Simulation results with PSPI CE showed that propagation delay time and cutoff toggle frequency of designed gate were 25ps and 200Hz, respectively. the designed gate exhibited superior properties to the recently reported HBT ECL and MESFET SCFL when considering the fan-out characteristics and noise margin.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.121-126
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• 1996

In this paper an MMIC VCO which can be used in a double conversion TV tuner is designed, fabricated and measured. The VCO is designed using the small signal method and fabricated using ETRI GaAs MMIC foundry. The 3x200$\mu$m gate width MESFET with 1$\mu$m gate length is used for an active device and MIM capacitors, spiral inductors, thin film resitors are used as passive elements. The VCO has output power of 10.95dBm at 1955 MHz with 5V bias voltage and 4V tuning voltage. The oscillation frequency change form 1947 MHz to 1964 MHz is obtaine dby an external varactor diode connected to the gate with a tuning voltage from 0 V to 6V.

• Journal of Power Electronics
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• v.10 no.3
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• pp.228-234
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• 2010

This paper investigates the conducted-noise characteristics of a digitally-controlled randomly-switched dc-dc converter. In order to investigate the effect of the suggested digital controller on the conducted-noise characteristics of a dc-dc converter, three factors have been studied: the field-programmable gate array (FPGA) clock speed, the randomization ratio percentage, and the effect of using a closed loop feedback controller. A field-programmable gate array is much more flexible than analog control circuits, has a lower cost, and can be used for power supply applications. A novel FPGA-based implementation has been suggested for obtaining the experimental validations and realizing the studied concepts. Furthermore, the experimental results have been discussed and design guidelines have been included.