• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.558-563
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• 2021

Quantum-Dot Cellular Automata is a next-generation nanocircular design technology that is drawing attention from many research organizations not only because it is possible to design efficient circuits by overcoming the physical size limitations of existing CMOS circuits, but also because of its energy-efficient features. In this paper, one of the existing digital circuits, T flip-flop circuit, is proposed using QCA. The previously proposed T flip-flops are designed based on the majority gate, so the circuits are complex and have long delays. Therefore, the design of the XOR gate-based T flip-flop using cell interaction reduces circuit complexity and minimizes latency. The proposed circuit is simulated using QCADesigner, and the performance is compared and analyzed with the existing proposed circuits.

• Journal of Practical Engineering Education
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• v.6 no.2
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.1-9
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• 1999

Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.16 no.6
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• pp.63-68
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• 2017

The purpose of this study is to improve the whitening phenomenon around the PET preform gate for blow molding. CAE analysis of plastic injection molding has been applied to design of preform shape and select the injection molding conditions. A ceramic insulation gate with lower thermal conductivity than metal is applied to improve the whitening phenomenon created around the gate in the injection molding process. According to the results of CAE analysis, the warpage deformation at the square corner was estimated to be about 0.34 mm at the bottom. From the results of the temperature history analysis, it was confirmed that the resin near the gate cooled more rapidly than the cavity. Ceramic insulated gates were fabricated to reduce the cooling rate and experiments were conducted to confirm the effectiveness of the whitening phenomenon improvement. As a result of the ceramic insulation gate experiment, it was confirmed that the whitening phenomenon was significantly reduced around the gate.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.54-65
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• 1999

As the integration ratio and operating speed increase, it has become an important problem to estimate the dissipated power during the design procedure to reduce th TTM(time to market). This paper proposed a prediction model for the maximum dissipated power of a CMOS logic gate. This model uses a calculating method. It was constructed by including the characteristics of MOSFETs, the operational characteristics of the gate, and the characteristics of the input signals. As the construction procedure, a maximum power estimation model for CMOS inverter was formed first, And then, a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. We designed several CMOS gates in layout level with $0.6{\mu}m$ design rule to apply both to HSPICE simulation and to the proposed models. The comparison between the two results showed that the gate conversion model and the power estimation model had within 5% and 10% of the relative errors, respectively. Those values show that the proposed models have sufficient accuracies. Also in calculation time, the proposed models were more than 30 times faster than HSPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.361-362
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• 2016

Presented in this paper is the design of a high voltage switch module made up of MOSFETs, pulse transformers and their gate driver circuits compactly fitted onto a single PCB module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier switch synchronization is also described in this paper. The stored energy in the capacitor bank of a 15kV, 4.5kJ/s peak power capacitor charger was discharged using the developed high voltage switch, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.19 no.6
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• pp.55-60
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• 2020

The injection molding technique is a processing method widely used for the production of plastic parts. In this study, the gate position, gate size, packing time, and melt temperature were optimized to minimize both the stress and deformation that occur during the injection molding process of medical suction device components. We used a central composite design and Latin hypercube sampling to acquire the data and adopted the response surface method as an approximation method. The efficiency of the optimization of the injection molding problem was determined by comparing the results of a genetic algorithm, sequential quadratic programming, and a non-dominant classification genetic algorithm.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.1 s.178
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• pp.159-165
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• 2006

Many rubber products are used in industrial products such as various hoses, rubber belts and oil seals etc. Especially, more then 200 rubber parts are used in the automobile, but design technology of these is largely dependent on Held experiences. These methods brought about too much time and cost in the developing procedures. However, with the help of recent rapid development of non-liner computer analysis, we can develop new sound products at low cost. Therefore in this study, optimizations of design variables such as location and number of gate in order to develop CLIP rubber product made of EPDM were performed by CAE in which Cross-WLF equations are adopted. The validity of proposed variables is evaluated by comparison with real forming results.