• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.62-69
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• 2012

Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

• IE interfaces
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• v.20 no.1
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• pp.69-78
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• 2007

We conduct an empirical study on RFID application to a real container terminal gate. The objective of this study is three-fold. The first is to design a new gate management process that applies RFID technology. For this purpose, we analyze current gate management process to find opportunities for improvement. The second is to verify the 433 and 900 MHz RFID technology in terms of the recognition rate of information contained in RFID tag under various conditions such as the speed of vehicle, the position of RFID tag and the tilt of RFID reader. We perform some experimental tests for this verification. Finally, we try to find suitable conditions for the speed of vehicle, the position of RFID tag and the tilt of RFID tag reader based on results of the experimental tests. Those findings are obtained with some ANOVA tests. Additionally, we summarize anticipated issues when applying RFID technology to the gate management process and possible solutions for the issues.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.

• Journal of Navigation and Port Research
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• v.30 no.5 s.111
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• pp.389-396
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• 2006

With the recent port environment, the integration of the separated berth is being actively progressed and the necessity of integration has been strengthening. Therefore, the application of existing gates have to review in order to reduce the truck turnaround time and to distribute the truck traffic volume in port container terminal. This paper analyzed the operation impact both the integrated gate and the separated gates. As the result of the analysis, this study suggests the separated gate system as an efficient design for gate operation considering integration of two individual berth.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.371-375
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• 2000

In this paper a new conductivity modulated power transistor called the Lateral Insulated Gated Bipolar Transistor which included n+ ring and p-channel gate is presented. A new lateral IGBT structure is proposed to suppress latch-up and to improve turn off time by imploying n+ ring and p-channel gate and verified by MEDICI. The simulated I-V characteristics at $V_{G}$=15V show that the latch up occurs at $V_{A}$=18V and 6.9$\times$10$^{-5}$ A/${\mu}{\textrm}{m}$ for the proposed LIGBT while the conventional LIGBT latches at $V_{A}$=1.3V and 1.96${\mu}{\textrm}{m}$10$^{-5A}$${\mu}{\textrm}{m}$. It is shown that turn off characteristic of new LIGBT is 8 times than that of conventional LIGBT. And noble LIGBT is not n+ buffer layer because that It includes p channel gate and n+ ring. Therefore Mask for the buffer layer isn’t needed. The concentration of n+ ring is and the numbers of n+ ring and p channel gate are three for the optimal design.n.n.n.n.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.196-197
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• 2006

In this paper, two types of vertical SIT(Static Induction Transistor) structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. First, a trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. Second, a trench gate-source region power SIT device is proposed to obtain more higher forward blocking voltage and forward blocking characteristics at the same size. The two proposed devices have superior electrical characteristics when compared to conventional device. In the proposed trench gate oxide power SIT, the forward blocking voltage is considerably improved by using the vertical trench oxide and the forward blocking voltage is 1.5 times better than that of the conventional vertical power SIT. In the proposed trench gate-source oxide power SIT, it has considerable improvement in forward blocking characteristics which shows 1500V forward blocking voltage at -10V of the gate voltage. Consequently, the proposed trench oxide power SIT has the superior stability and electrical characteristics than the conventional power SIT.

• 한국IT서비스학회:학술대회논문집
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• 2006.11a
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• pp.532-539
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• 2006

We conduct an empirical study on RFID application to a real container terminal gate. The objective of this study is three-fold. The first is to design a new gate management process that applies RFID technology. For this purpose, we analyze current gate management process to find opportunities for improvement. The second is to verify the 433 and 900 Mhz RFID technology in terms of the recognition rate of information contained in RFID tag under various conditions such as the speed of vehicle, the position of RFID tag and the tilt of RFID reader. We perform some experimental tests for this verification. Finally, we try to find suitable conditions for the speed of vehicle, the position of RFID tag and the tilt of RFID tag reader based on results of the experimental tests. Those findings are obtained with some ANOVA tests. Additionally, we summarize anticipated issues when applying RFID technology to the gate management process and possible solutions for the issues.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.59-64
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• 2016

In this paper, a 10W GaN MMIC was designed and fabricated using the Ku-band SSPA module. For Design and fabrication of the SSPA module using Rogers(RO4003C) substrate was used for Branch-line structure. SSPA modules on budget Divider/Combiner was designed and fabricated less than the maximum insertion loss - 0.7dB. In addition, because it must be applied to the structural nature of GaN MMIC Gate Bias-Drain Bias circuit was implemented to apply the Gate-Drain sequential circuit, implemented the RF Power Detect, Temperature Detect, HPA On/Off function. Design and fabrication Ku-band SSPA Module got the measurement results that satisfy a maximum output of 15.6W, Gain 45.7dB, 19.0% efficiency.

• Journal of IKEEE
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• v.25 no.3
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• pp.473-478
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• 2021

Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.