• Communications of Mathematical Education
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• v.31 no.3
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• pp.279-290
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• 2017

This study proposes a self learning material for understanding the key contents of Galois theory. This material is for teachers who have learned algebraic structures like group, field, and vector space which are related with Galois theory but do not clearly understand how algebraic structures are related with the solvability of polynomials and school mathematics. This material is likely to help them to overcome such difficulties. Even though proposed material is used mainly for self learning, the teachers may be helped once or twice by some professionals. In this article, two expressions 'solvability of polynomial' and 'solvability of equation' have the same meaning and 'teacher' means in-service mathematics teacher.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1774-1779
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• 2005

This paper propose the design method of the constructing the digital logic systems over galois fields using by the galois field decision diagram(GFDD) that is based on the graph theory. The proposed design method is as following. First of all, we discuss the mathematical properties of the galois fields and the basic properties of the graph theory. After we discuss the operational domain and the functional domain, we obtain the transformation matrixes, $\psi$GF(P)(1) and $\xi$GF(P)(1), in the case of one variable, that easily manipulate the relationship between two domains. And we extend above transformation matrixes to n-variable case, we obtain $\psi$GF(P)(1) and $\xi$GF(P)(1). We discuss the Reed-Muller expansion in order to obtain the digital switching functions of the P-valued single variable. And for the purpose of the extend above Reed-Muller expansion to more two variables, we describe the Kronecker product arithmetic operation.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.503-508
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• 2004

This paper proposes an efficient computation method for fixed and mixed polarity Reed -Muller function vector over Galois field GF(p). Function vectors of fixed polarity Heed Muller function with single variable can be generated by proposed method. The n-variable function vectors can be calculated by means of the Kronecker product of a single variable function vector corresponding to each variable. Thus, all fixed and mixed polarity Reed-Muller function vectors are calculated directly without using a polarity function vector table or polarity coefficient matrix.

• Journal of Communications and Networks
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• v.12 no.5
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• pp.406-410
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• 2010

This paper presents an approach to the construction of non-binary quasi-cyclic (QC) low-density parity-check (LDPC) codes based on multiplicative groups over one Galois field GF(q) and Euclidean geometries over another Galois field GF($2^S$). Codes of this class are shown to be regular with girth $6{\leq}g{\leq}18$ and have low densities. Finally, simulation results show that the proposed codes perform very wel with the iterative decoding.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.13-20
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• 2005

For Modern Consumer and Communication Elecronic Devices, Always Error Protecting HW and SW is used. The Core is RS(Reed Solomon) Codec in Galois Field GF($2^8$). Here New 2 to 3 Symbol RS Decoder Design and Encoder design Method using Normalized error position Value is described. Examples are given to show the methods are working well.

• Journal of the Chungcheong Mathematical Society
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• v.30 no.1
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• pp.77-102
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• 2017

As an analogy of $Poincar{\acute{e}}$ series in the space of modular forms, T. Ono associated a module $M_c/P_c$ for ${\gamma}=[c]{\in}H^1(G,R^{\times})$ where finite group G is acting on a ring R. $M_c/P_c$ is regarded as the 0-dimensional twisted Tate cohomology ${\hat{H}}^0(G,R^+)_{\gamma}$. In the case that G is the Galois group of a Galois extension K of a number field k and R is the ring of integers of K, the vanishing properties of $M_c/P_c$ are related to the ramification of K/k. We generalize this to arbitrary n-dimensional twisted cohomology of the ring of integers and obtain the extended version of theorems. Moreover, some explicit examples on quadratic and biquadratic number fields are given.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.1
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• pp.42-47
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• 1985

An efficient logic circuit for realizing the function which has output of 1 diagonaly and design for multivalued logic circuit using with ROM structure which has two output at once are presented. The circuits presented are suited for the circuit design of a symmetric multivalued truth tables and the circuit design of multivalued truth tables with many independent variables. Also, they are applied to the multivalued truth tables of Galois field(GF).

• Journal of Power System Engineering
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• v.8 no.1
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• pp.62-68
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• 2004

This paper describes a fault tolerant control in distributed PLC(Programmable Logic Controller) system to ensure reliability of controllers which have some faults simultaneously. First, the behavior of PLC is modeled as discrete expressions using Galois field. Then, we design the control laws for additional spare controllers to generate parity code with two dimensions. Finally, the algorithm for estimating normal output instead of abnormal output from the controllers with fault is suggested. Comparing to the traditional duplication method, the suggested method can reduce the number of spare controllers significantly to ensure control reliability. This method will be applied to an automatic system in order to increase reliability. Also, it can improve cost performance of the system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.355-361
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• 2001

유한체(Galois Field) 상에서의 곱셈(multiplication)을 구현하는 방법은 크게 병렬 곱셈기(parallel multiplier)와 직렬 곱셈기(serial multiplier)로 나누어질 수 있는데, 구현시 하드웨어 면적을 작게 차지한다는 장점 때문에 직렬 곱셈기가 널리 사용된다. 하지만 이 직렬 곱셈기를 이용하여 계산을 하기 위해서는 병렬 곱셈기에 비해 많은 시간이 필요하게 된다. 직렬기법과 병렬기법의 결합이 이를 보완할 수 있게 된다. 본 논문에서는 복잡도는 직렬 곱셈기와 큰 차이가 없으면서 연산시간을 줄인 곱셈기*(multiplier)를 제안하였다. 이 곱셈기를 사용하면 복잡도는 크게 늘어나지 않았으면서 유한체 상에서의 곱셈을 하는데 필요한 시간을 줄이는 효과를 얻을 수 있다.