• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.2
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• pp.93-100
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• 2022

In this paper, we propose a machine learning-based method for supporting resource management of IoT software platforms in a multi-modal sensing scenario. We assume that an IoT device installed with a oneM2M-compatible software platform is connected with various sensors such as PIR, sound, dust, ambient light, ultrasonic, accelerometer, through different embedded system interfaces such as general purpose input output (GPIO), I2C, SPI, USB. Based on a collected dataset including CPU usage and user-defined priority, a machine learning model is trained to estimate the level of nice value required to adjust according to the resource usage patterns. The proposed method is validated by comparing with a rule-based control strategy, showing its practical capability in a multi-modal sensing scenario of IoT devices.

• Proceedings of the Korean Society of Computer Information Conference
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• 2022.07a
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• pp.407-408
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• 2022

본 논문에서는 AIoT를 위한 비주얼 블록 코딩 도구를 설계하였다. AI 블록 코딩이 가능한 EduB 플랫폼에 피지컬 컴퓨팅을 가능하게 하는 모듈을 추가함으로써 블록을 사용한 쉬운 피지컬컴퓨팅 코딩과 AIoT 코딩이 가능하다. 도구는 WebSocket과 Wifi를 사용해 EduB와 타겟보드인 RaspberryPi의 무선 통신을 하며, 블록으로 생성된 코드를 RaspberryPi 내부에서 실행하여 GPIO와 SenseHAT을 제어할 수 있게 하였다. 따라서, 코딩 결과를 콘솔 출력이나 그래프로만 확인할 수 있어 정적이던 AI 교육을 LED나 모터를 제어해 동적으로 결과를 확인할 수 있게 하여 흥미와 관심을 유발할 수 있도록 한다.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.111-120
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• 2016

Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

• The KIPS Transactions:PartD
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• v.11D no.2
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• pp.443-452
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• 2004

The paper presents an intelligent space management system for ubiquitous computing. The system is basically a home/office automation system that could control light, electronic key, and home appliances such as TV and audio. On top of these basic capabilities, there are four elegant features in the system. First, we can access the system using either a cellular Phone or using a browser on the PC connected to the Internet, so that we control the system at any time and any place. Second, to provide more human-oriented interface, we integrate voice recognition functionalities into the system. Third, the system supports not only reactive services but also proactive services, based on the regularities of user behavior. Finally, by exploiting embedded technologies, the system could be run on the hardware that has less-processing power and storage. We have implemented the system on the embedded board consisting of StrongARM CPU with 205MHz, 32MB SDRAM, 16MB NOR-type flash memory, and Relay box. Under these hardware platforms, software components such as embedded Linux, HTK voice recognition tools, GoAhead Web Server, and GPIO driver are cooperated to support user-friendly intelligent space.

• The Journal of the Acoustical Society of Korea
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• v.28 no.3
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• pp.229-238
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• 2009

This paper describes a sound engine of Korean traditional instruments, which are the Gayageum and Taepyeongso, by using a TMS320F2812. The Gayageum and Taepyeongso models based on commuted waveguide synthesis (CWS) are required to synthesize each sound. There is an instrument selection button to choose one of instruments in the proposed sound engine, and thus a corresponding sound is produced by the relative model at every certain time. Every synthesized sound sample is transmitted to a DAC (TLV5638) using SPI communication, and it is played through a speaker via an audio interface. The length of the delay line determines a fundamental frequency of a desired sound. In order to determine the length of the delay line, it is needed that the time for synthesizing a sound sample should be checked by using a GPIO. It takes $28.6{\mu}s$ for the Gayageum and $21{\mu}s$ for the Taepyeongso, respectively. It happens that each sound sample is synthesized and transferred to the DAC in an interrupt service routine (ISR) of the proposed sound engine. A timer of the TMS320F2812 has four events for generating interrupts. In this paper, the interrupt is happened by using the period matching event of it, and the ISR is called whenever the interrupt happens, $60{\mu}s$. Compared to original sounds with their spectra, the results are good enough to represent timbres of instruments except 'Mu, Hwang, Tae, Joong' of the Taepyeongso. Moreover, only one sound is produced when playing the Taepyeongso and it takes $21{\mu}s$ for the real-time playing. In the case of the Gayageum, players usually use their two fingers (thumb and middle finger or thumb and index finger), so it takes $57.2{\mu}s$ for the real-time playing.

• Journal of the Korea Convergence Society
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• v.7 no.1
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• pp.9-15
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• 2016

In this paper, we describe the design of a high speed data acquisition system(DAS) with STM32 processor based on Cortex-M4. The system is used for the sensor devices to collect raw data on production lines at factory and send them to the servo computer in real time. The system is designed for multi functions with universal asynchronous receiver and transmitter(UART), analog to digital converter(ADC), digital to analog converter(DAC), and general purpose input output(GPIO). those are well tested for various data acquisition and high speed motor control in real time.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.07a
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• pp.427-428
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• 2019

칠교놀이는 해외에서는 Tangram이라고 불리며 아주 예전부터 전해져 내려오는 세계적인 놀이이다. 친구와 여럿이서 놀이를 할 수 있을 뿐만아니라 혼자서도 즐길 수 있다. 칠교놀이는 특히 창의력 향상에 도움을 주는데 이번 논문에서는 혼자서 쉽게 칠교놀이를 즐길 수 있도록 비전시스템과 라즈베리파이를 이용해서 칠교를 카메라로 인식해 성공하면 보상으로 사탕을 지급하는 놀이를 개발해 보았다. 자판기에 동전을 넣으면, 게임을 시작해서 칠교놀이의 문제를 하나씩 맞출 때 마다 사탕 한 개가 지급되는 방식으로 4차산업혁명 시대에 걸맞는 재미있는 칠교놀이 게임을 만들어 보았다. 본 논문은 OPENCV라이브러리와 라즈베리파이 GPIO라이브러리를 사용하였다. 사용한 부품은 웹캠, 초음파 센서, 서보모터이다. 라즈베리파이를 서버로 설정하고, PC를 클라이언트로 설정하여 서로 데이터를 주고 받을 수 있게 하였다. 라즈베리파이에 OPENCV를 설치하지 않은 이유는 OPENCV가 꽤 높은 사양이 필요하다고 판단하여 비전영상처리는 PC(클라이언트)에서 진행하고, 게임의 진행상황(정답의 여부)을 라즈베리파이(서버)에 보내는 방식으로 정하였다. 반대로 라즈베리파이에서도 동전의 투입 유무를 판단하여 PC(클라이언트)에 게임 시작 신호를 보내는 방식으로 설정하였다. 언어는 라즈베리파이와 PC둘다 Pythond으로 구현하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.639-642
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• 2009

LN2440SBC 임베디드 보드는 ARM 코어 방식의 S3C2440A CPU를 가진 임베디드 컴퓨터 시스템이다. 이 시스템에 부착한 터치스크린 기능을 가진 TFT LCD 키트인 LP35의 구동을 위해서는 ARM 코어, LCD 컨트롤러, 그리고 LCD 장치와의 통신을 위한 SPI(serial peripheral interface)의 초기화와 LCD 화면에 이미지, 선, 도형 같은 것들의 출력을 가능하게 해주는 그래픽스 라이브러리 함수들이 필요하다. 본 논문은 이같은 기능들을 가지는 LP35를 위한 드라이버의 구현 방법을 기술한다. 특히, 드라이버 구동을 위한 초기화 방법과 화면 출력 기능들의 구현을 위해 필요한 픽셀 디스플레이 함수의 구현에 중점을 두어 설명한다. 또한 픽셀 디스플레이 함수를 이용한 기본 그래픽스 라이브러리 함수들에 대해 설명한다. 드라이버의 초기화를 위해서는 클럭 속도 설정, 범용 입출력 핀(GPIO)을 LCD와 SPI 용으로의 할당. SPI의 마스터/슬레이브 및 보오 레이트 설정, LCD 컨트롤러 레지스터 설정을 통한 LCD 기능 선택. 그리고 SPI를 통한 LCD 장치로의 파워 온(power on) 명령 전달 등이 수행된다.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.76-81
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• 2024

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.