• Proceedings of the Korean Information Science Society Conference
• /
• 2002.04a
• /
• pp.892-894
• /
• 2002

본 논문은 유한 체 GF(/2 sup m/)상에서 A$B^2$연산을 위해 AOP(All One Polynomial)에 기반한 새로운 MSB(Most Significant bit) 유선 알고리즘을 제시하고, 제시한 알고리즘에 기반하여 병렬 입출력 세미시스톨릭 구조를 제안한다. 제안된 구조는 표준기저(standard basis)에 기반하고 모듈라(modoular) 연산을 위해 다항식의 계수가 모두 1인 m차의 기약다항식 AOP를 사용한다. 제안된 구조에서 AND와 XOR게이트의 딜레이(deray)를 각각 /D sub AND$_2$/와/D sub XOR$_2$/라 하면 각 셀 당 임계경로는 /D sub AND$_2$+D sub XOR/이고 지연시간은 m+1이다. 제안된 구조는 기존의 구조보다 임계경로와 지연시간 면에서 보다 효율적이다. 또한 구조 자체가 정규성, 모듈성, 병렬성을 가지기 때문에 VLSI 구현에 효율적이다. 더욱이 제안된 구조는 유한 체상에서 지수 연산을 필요로 하는 Diffie-Hellman 키 교환 방식, 디지털 서명 알고리즘 및 EIGamal 암호화 방식과 같은 알고리즘을 위한 기본 구조로 사용할 수 있다. 이러한 알고리즘을 응용해서 타원 곡선(elliptic curve)에 기초한 암호화 시스템(Cryptosystem)의 구현에 사용될 수 있다.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.16 no.2
• /
• pp.105-111
• /
• 2006

Cryptographic application and coding theory require operations in finite field $GF(2^m)$. In such a field, the area and time complexity of implementation estimate by memory and time delay. Therefore, the effort for constructing an efficient multiplier in finite field have been proceeded. Massey-Omura proposed a multiplier that uses normal bases to represent elements $CH(2^m)$ [11] and Agnew at al. suggested a sequential multiplier that is a modification of Massey-Omura's structure for reducing the path delay. Recently, Rayhani-Masoleh and Hasan and S.Kwon at al. suggested a area efficient multipliers for modifying Agnew's structure respectively[2,3]. In [2] Rayhani-Masoleh and Hasan proposed a modified multiplier that has slightly increased a critical path delay from Agnew at al's structure. But, In [3] S.Kwon at al. proposed a modified multiplier that has no loss of a time efficiency from Agnew's structure. In this paper we will propose a multiplier by modifying Rayhani-Masoleh and Hassan's structure and the area-time complexity of the proposed multiplier is exactly same as that of S.Kwon at al's structure for type-II optimal normal basis.

• Journal of IKEEE
• /
• v.7 no.1 s.12
• /
• pp.9-15
• /
• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.10a
• /
• pp.190-192
• /
• 2018

This paper describes a design of an elliptic curve cryptography (ECC) processor that supports five pseudo-random curves and five Koblitz curves over binary field defined by the NIST standard. The ECC processor adopts the Lopez-Dahab projective coordinate system so that scalar multiplication is computed with modular multiplier and XORs. A word-based Montgomery multiplier of $32-b{\times}32-b$ was designed to implement ECCs of various key lengths using fixed-size hardware. The hardware operation of the ECC processor was verified by FPGA implementation. The ECC processor synthesized using a 0.18-um CMOS cell library occupies 10,674 gate equivalents (GEs) and 9 Kbits RAM at 100 MHz, and the estimated maximum clock frequency is 154 MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.3
• /
• pp.191-200
• /
• 2002

In this paper, we present the method transforming the interval functions into the truncated difference functions for multi-variable multi-valued functions and implementing the truncated difference functions to the multiple valued logic circuits with uniform patterns using the current mirror circuits and the inhibit circuits by current-mode CMOS. Also, we apply the presented methods to the implementation of circuits for additive truth table of 2-variable 4-valued MOD(4) and multiplicative truth table of 2-variable 4-valued finite fields GF(4). These circuits are simulated under 2${\mu}{\textrm}{m}$ CMOS standard technology, 15$mutextrm{A}$ unit current, and 3.3V power supply voltage using PSpice. The simulation results have shown the satisfying current characteristics. Both implemented circuits using current-mode CMOS have the uniform Patterns and the regularity of interconnection. Also, it is expansible for the variables of multiple valued logic functions and are suitable for VLSI implementation.

• Journal of the Korea Society of Computer and Information
• /
• v.28 no.2
• /
• pp.69-75
• /
• 2023

Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.23 no.3
• /
• pp.359-370
• /
• 2013

Lin and Chan proposed a reversible secret image sharing scheme in 2010. The advantages of their scheme are as follows: the low distortion ratio, high embedding capacity of shadow images and usage of the reversible. However, their scheme has some problems. First, the number of participants is limited because of modulus prime number m. Second, the overflow can be occurred by additional operations (quantized value and the result value of polynomial) in the secret sharing procedure. Finally, if the coefficient of (t-1)th degree polynomial become zero, (t-1) participants can access secret data. In this paper, an improved reversible secret image sharing scheme which solves the problems of Lin and Chan's scheme while provides the low distortion ratio and high embedding capacity is proposed. The proposed scheme solves the problems that are a limit of a total number of participants, and occurrence of overflow by new polynomial operation over GF($2^8$). Also, it solve problem that the coefficient of (t-1)th degree polynomial become zero by fixed MSB 4-bit constant. In the experimental results, PSNR of their scheme is decreased with the increase of embedding capacity. However, even if the embedding capacity increase, PSNR value of about 45dB or more is maintained uniformly in the proposed scheme.

• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.129-131
• /
• 2004

Elliptic Curve Cryptography (ECC) coprocessors support massive scalar multiplications of a point. We research the design for multi-segment multipliers in fixed-size ECC coprocessors using the multi-segment Karatsuba algorithm on GF($2^m$). ECC coprocessors of the proposed multiplier is verified on the SoC-design verification kit which embeds ALTERA EXCALIBUR FPGAs. As a result of our experiment, the multi-segment Karatsuba multiplier, which has more efficient performance about twice times than the traditional multi-segment multiplier, can be implemented as adding few H/W resources. Therefore the multi-segment Karatsuba multiplier which satisfies performance for the cryptographic algorithm, is adequate for a low cost embedded system, and is implemented in the minimum area.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.10 no.1
• /
• pp.3-11
• /
• 2000

AAL-1에서는 (128, 124) Reed-Solomon부호를 사용한 인터리버 및 디인터리버에 의해 ATM 셀에서 발생하는 오류를 정정하고 있다. Reed-Solomon부호의 복호법 중 직접복호법은 오류위치다항식의 계산없이 오류위치와 오류치를 알 수 있으며 유한체 GF(2m)의 표현에서 정규기저를 사용하면 곱셈과 나눗셈을 단순한게 비트 이동만으로 처리할 수 있다. 직접복호법과 정규기저를 사용하여 ATM 적응계층에 적용 가능한 (128, 124) Reed-Solomon부호의 복호기를 설계하고 VHDL로 시뮬레이션 하였으며 이 복호기는 동일한 복호회로에 의해 둘 또는 하나의 심벌에 발생한 오류를 정정할 수 있다.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.18 no.1
• /
• pp.1-9
• /
• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.