• Title/Summary/Keyword: GCNMOS

Search Result 1, Processing Time 0.013 seconds

A Study on GCNMOS-based ESD Protection Circuit Using Floating-Body Technique With Low Trigger Voltage (Floating-Body기술을 이용한 낮은 트리거 전압을 갖는 GCNMOS 기반의 ESD 보호회로에 관한 연구)

  • Jeong, Jun-Mo
    • Journal of IKEEE
    • /
    • v.21 no.2
    • /
    • pp.150-153
    • /
    • 2017
  • In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.