• Bulletin of the Korean Space Science Society
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• 2009.10a
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• pp.25.2-25.2
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• 2009

한국천문연구원 한국우주전파관측망(Korean VLBI Network, KVN)에서 도입하여 시험운용중인 VLBI 상관서브시스템(VLBI Correlation Subsystem, VCS)은 한일공동 VLBI 상관기(Korea-Japan Joint VLBI Correlator, KJJVC)의 핵심 장비로서, 최대 16 관측국의 관측국 당 최대 8Gbps의 데이터를 처리할 수 있는 상관처리장치이다. VCS의 상관처리 결과는 총 4회선의 10GbE 광케이블을 통하여 UDP 프로토콜로 출력된다. 이 상관처리 결과는 광케이블 하나당 8개씩 총 32개의 상관 처리 블록(correlation block)으로 구성되며, 최대 출력속도는 1.4 GBytes/sec이다. 이 출력은 초고속 대용량 자료저장 시스템(Peta-scale Epoch Data Archive, PEDA)을 이용하여 저장하고 후속 자료처리를 위해 가공된다. PEDA는 총 4대의 고성능 자료 전송 및 저장 서버(writing server) 및 대용량 하드디스크 어레이로 구성된다. 상관처리 과정에 맞추어 PEDA의 writing 서버를 연계하여 제어하는 자료 전송 및 저장 제어 소프트웨어를 개발하였다. 이 소프트웨어는 핵심이 되는 전송 및 저장 프로세서와 이를 제어하는 제어프로세서로 구성된다. 전송 및 저장 프로세서는 개개의 상관 처리 블록에 대한 전송과 저장을 전담한다. 제어 프로세서는 총 32개의 상관 처리 블록을 처리하기 위하여 전송 및 저장 프로세스를 32개를 실행하고 각각의 상관 처리 블록에 해당하는 개별파라미터를 전달하는 전체적인 제어를 담당한다. 이 연구에서는 이 자료전송 및 저장 제어 소프트웨어의 설계 구성과 테스트 내용을 소개한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.41-44
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• 2013

As appearance of high-quality service such as UDTV application, high-speed and high-capacity communication services are required. For this, communication systems increase the data processing speed and use various error correction techniques. In this paper, we implement the Viterbi decoder applied in 1000BASE-T with 4 pairs UTP cable. The minimum operating speed of the Viterbi decoer should be more than 125 MHz because 125 MHz PAM-5 signal is transmitted on each pair of cables in 1000BASE-T. To do this, we implement the decoder by using the pipeline and parallel processing and verify the operation with 125 MHz by using a logic analyzer. Finally, we will show that the decoder recovers the original data for the added random error data.

• International Area Studies Review
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• v.13 no.1
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• pp.103-122
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• 2009

The paper is basically designed to investigate any existence of co-movement among foreign exchange market, goods market, and monetary market implemented by relative PPP and interest rate parity. And, rational expectation and GARCH-M model are employed for an empirical application. The result revealed that since the co-movement among the markets is hardly found, an efficiency of foreign exchange market is independent from any shocks from the goods market and the monetary market. Whereas, the exchange rate is strongly effected by a real interest rate parity. To this end, the real interest rate should be a key policy instrument to stabilize the foreign exchange market.

• Journal of Animal Science and Technology
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• v.46 no.4
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• pp.537-546
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• 2004

Adiponectin is adipocyte complement-related protein which is highly specialized to play important roles in metabolic and honnonal processes. This protein, called GBP-28, AdipoQ, and Acrp30, is encoded by the adipose most abundant gene transcript 1 (APM1) which locates on human chromosome 3q27 and mouse chromosome 16. In order to determine chromosomal localization of the porcine APM1, we carried out PCR analysis using somatic cell hybrid panel as well as porcine whole genome radiation hybrid (RH) panel. The result showed that the porcine APM1 located on chromosome 13q41 or 13q46-49. These locations were further investigated with the two point analysis of RH panel, revealed the most significant linked marker (LOD score 20.29) being SIAT1 (8 cRs away), where the fat-related QTL located. From the SSCP analysis of APM1 using 8 pig breeds, two distinct SSCP types were detected from K~ native and Korean wild pigs. The determined sequences in Korean native and Korean wild pigs showed that two nucleotide positions (T672C and C705G) were substituted. The primary sequence of the porcine APM1 has 79 to 87% identity with those of human, mouse, and bovine APM1. The domain structures of the porcine APM1 such as signal sequence, hypervariable region, collagenous region. and globular domain are also similar to those of mammalian genes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.71-78
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• 2005

In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.245-250
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• 2015

We have developed an optical video transmission device for HD-SDI signal transmission. The optical transmitter/receiver unit operates at DC 5 volt and small enough to be attaced near surveillance camera. They have internal voltage regulating circuits to supply 3.3V to other circuits inside the unit. The optical transmitter is composed of cable driver, laser diode driver, and laser diode. The optical receiver is composed of photodiode, limiting amp, and cable equalizer. The wavelength of the trasmitter was 1.3 um, and optical power was -5dBm, and the speed was 1.485Gbps. The receiver sensitivity was -23 dBm. We confirmed that the optical device can transmit HD-SDI video through 30 km optical fiber without any interruption.