• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.6
• /
• pp.199-208
• /
• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.30-31
• /
• 2008

As the power density and switching frequency increase, thermal analysis of power electronics system becomes imperative. The analysis provides valuable information on the semiconductor rating, long-term reliability. In this paper, thermal distribution of the Non Punchthroug(NPT) Insulated Gate Bipolar Transistor with heatsink areas has been studied. For analysis of thermal distribution, we obtained results by using finite element simulator, ANSYS and compared with experimental data by thermocam.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.11
• /
• pp.1434-1444
• /
• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.2
• /
• pp.120-124
• /
• 2000

In this paper, the effects of trap distribution on switching characteristis of a lateral insulated gate bipolar transistor (LIGBT) are investigated. The simulations are performed in order to to analyze the effect of the positon, width and concentration of trap distribution model with a reduced minority carrier lifetime using 2D device simulator MEDICI. The turn off time for the proposed LIGBT model A with the trap injection is 0.8$mutextrm{s}$. These results indicate the improvement of about 2 times compared with the conventional LIGBT. It is shown that the trap distribution model is very effective to reduce the turn-off time with a little increasing of on-state voltage drop.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.147-148
• /
• 2005

As the power density and switching frequency increase, thermal analysis of power electronics system becomes imperative. The analysis provides valuable information on the semiconductor rating, long-term reliability and efficient heat-sink design. In this paper, thermal distribution of the Insulated Gate Bipolar Transistor Module has been studied with different conditions and heat sink materials. For analysis of thermal distribution, we obtained results by using finite element simulator, Ansys.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.172-173
• /
• 2007

As the power density and switching frequency increase, thermal analysis of power electronics system becomes imperative. The thermal analysis provides valuable information on the semiconductor rating, long-term reliability. In this paper, thermal distribution of the Non Punchthrough(NPT) Insulated Gate Bipolar Transistor has been studied. For analysis of thermal distribution, we obtained experimental and simulation results by using finite element simulator, Ansys and by using photographic infrared thermometer, we compared experimental date with simulation result. and got good agreement. Also this paper provided thermal distribution of IGBT connected to heat sinks. and this results will be good information to design optimal heat sink for IGBT.

• The Journal of Korea Robotics Society
• /
• v.16 no.3
• /
• pp.245-249
• /
• 2021

In this paper, we present novel simulation contents for drone racing and autonomous flight of drone. With Depth camera and SLAM, we conducted mapping 3 dimensional environment through RTAB-map. The 3 dimensional map is represented by point cloud data. After that we recovered this data in Unreal Engine. This recovered raw data reflects real data that includes noise and outlier. Also we built drone racing contents like gate and obstacles for evaluating drone flight in Unreal Engine. Then we implemented both HITL and SITL by using AirSim which offers flight controller and ROS api. Finally we show autonomous flight of drone with ROS and AirSim. Drone can fly in real place and sensor property so drone experiences real flight even in the simulation world. Our simulation framework increases practicality than other common simulation that ignore real environment and sensor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.131-131
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.1
• /
• pp.311-323
• /
• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Journal of IKEEE
• /
• v.19 no.2
• /
• pp.265-270
• /
• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.